FIFO module, deskew circuit and rate matching circuit having...

Details FIFO module, deskew circuit and rate matching circuit having... FIFO module, deskew circuit and rate matching circuit having...

2006-08-15

2006-08-15

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

07093061

ABSTRACT:
A first-in-first-out (FIFO) module is disclosed. The FIFO module includes multiple individually addressable memory locations, a write pointer, a read pointer and at least additional pointer. The write pointer is connected to the memory bank for addressing a first memory location to write a datum on an input data bus into the first memory location. The read pointer is connected to the memory bank for addressing a second memory location to read a datum stored therein onto an output data bus. The at least one additional pointer is connected to the memory bank for addressing a third memory location to read a datum stored therein. A deskew circuit and a rate matching circuit which utilize the FIFO module, and a deskew method are also disclosed.

REFERENCES:
patent: 6873180 (2005-03-01), Bentz
patent: 2005/0066120 (2005-03-01), Ohta et al.

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