FIFO memory system determining full empty using predetermined ad

Details FIFO memory system determining full empty using predetermined ad FIFO memory system determining full empty using predetermined ad

1995-10-10

1998-05-26

Ellis, Richard L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711217, G06F 1320

Patent

active

057581924

ABSTRACT:
A structure and method for determining whether a first in, first out (FIFO) memory is empty or full when the read address of the memory equals the write address of the memory. The read and write addresses are individually incremented, each in a predetermined circular sequence. The circular sequence is divided at least three segments. Portions of the read and write addresses are encoded to indicate the segments in which the read and write addresses are located. These encoded address portions are decoded to determine the relative segment positions of the read and write addresses. If the read address is in the segment prior to the write address, a DIRECTION signal is set to a first state. If the write address is in the segment prior to the read address, the DIRECTION signal is set to a second state. When the read address equals the write address, the state of the DIRECTION signal is used to determine whether the memory is empty or full. If the DIRECTION signal is in the first state, the memory is empty. If the DIRECTION signal is in the second state, the memory is full.

REFERENCES:
patent: 5088061 (1992-02-01), Golnabi et al.
patent: 5220586 (1993-06-01), Tai
patent: 5381126 (1995-01-01), McClure et al.
patent: 5426756 (1995-06-01), Shyl et al.
patent: 5555524 (1996-09-01), Castellano

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