FIFO memory system

Details FIFO memory system FIFO memory system

1993-06-03

1994-10-25

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Serial read/write

34082505, 34082506, 395425, 36523003, G11C 700, G06F 1200

Patent

active

053595688

ABSTRACT:
This invention relates to a FIFO memory system (10) comprising a plurality of FIFO memories (20) for handling transmission queues in a serial digital communication system. The memory system comprises a plurality of blocks of memory (20a-c, 21a-e), each of the plurality of FIFO memories being assigned a block (20a) of the plurality of blocks of memory, the unassigned blocks of memory forming a block pool (21a-e). The memory system further comprises memory management means (LLT, PT) for adding at least one of the unassigned blocks of memory from the block pool to a FIFO memory on writing to the FIFO memory whereby the size of the FIFO memory is selectably variable, and for returning a block of memory from a FIFO memory to the block pool once the contents of the block of memory have been read.

REFERENCES:
patent: 4652874 (1987-03-01), Loyer
patent: 5047917 (1991-09-01), Athas et al.
patent: 5233701 (1993-08-01), Nakata

Affiliated with

Also associated with

Rating

FIFO memory system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FIFO memory system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FIFO memory system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-140744