FIFO memory in which number of bits subject to each data read/wr

Details FIFO memory in which number of bits subject to each data read/wr FIFO memory in which number of bits subject to each data read/wr

1993-05-10

1995-03-07

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

36518912, 365240, G11C 700

Patent

active

053964608

ABSTRACT:
A FIFO memory is disclosed which includes a plurality of memory cells, a mode circuit designating a first or a second mode in response to a mode signal supplied thereto, a selection circuit for selecting a first number of the memory cells each time a clock signal is generated in the first mode and for selecting a second number of the memory cells each time the clock signal is generated in the second mode, the first number being different from the second number, and an access circuit for accessing the selected memory cells to write data thereinto and to read data therefrom, whereby the number of memory cells to accessed is changeable in the mode to be performed.

REFERENCES:
patent: 5142494 (1992-08-01), D'Luna
patent: 5200925 (1993-04-01), Morooka
patent: 5272675 (1993-12-01), Kobayashi

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