FIFO memory devices having multi-port cache and extended...

Details FIFO memory devices having multi-port cache and extended... FIFO memory devices having multi-port cache and extended...

2005-03-29

2005-03-29

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S120000, C710S052000

Reexamination Certificate

active

06874064

ABSTRACT:
A FIFO memory device includes a multi-port cache memory and an extended capacity memory (e.g., SRAM). The multi-port cache memory includes a data input port, a data output port, a first memory port that is configured to pass write data to the extended capacity memory during memory write operations and a second memory port that is configured to receive read data from the extended capacity memory during memory read operations. The multi-port cache memory includes at least a data input register and a multiplexer that is responsive to at least one path signal. The multiplexer is configured to enable a first memory path that routes first data from the second memory port to the data output port during first FIFO read operations that occur when the FIFO memory device is filled beyond a threshold level. The multiplexer is also configured to block the first memory path and enable a direct path that routes second data from the data input register to the data output port during second FIFO read operations that occur when the FIFO memory device is almost empty.

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