FIFO memory device including circuit for generating flag signals

Details FIFO memory device including circuit for generating flag signals FIFO memory device including circuit for generating flag signals

1986-09-18

1989-07-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Serial read/write

365 78, 365236, 365239, 36518902, 36518912, G11C 700, G11C 1900, G11C 800

Patent

active

048478121

ABSTRACT:
A FIFO memory device facilitates transfer of data between a host CPU and a peripheral device in one of a number of modes. In one mode the FIFO memory device functions as two FIFO memories, one for passing data from the host CPU to the peripheral device, and one for passing data to the host CPU from the peripheral device. In another mode, the FIFO memory device functions as a single FIFO which facilitates passing data from the host CPU to the peripheral device or from the peripheral device to the host CPU. The FIFO includes two RAMs addressed by a set of address counters. Of importance, the host CPU can bypass the address counters to directly address each RAM, thereby reading data from or writing data to either RAM regardless of the state of the address counters. The FIFO also includes a pair of registers for receiving data from the host CPU. The contents of the address counters are compared with the contents of the registers so that a programmable flag signal can be generated by the FIFO to indicate when the contents of the address counters equal the contents of the registers.

REFERENCES:
patent: 3553651 (1971-01-01), Bird et al.
patent: 3629857 (1971-12-01), Faber
patent: 4062059 (1977-12-01), Suzuki et al.
patent: 4093995 (1978-06-01), Smith et al.
patent: 4125870 (1978-11-01), Suzuki et al.
patent: 4138732 (1979-02-01), Suzuki et al.
patent: 4145755 (1979-03-01), Suzuki et al.
patent: 4161778 (1979-07-01), Getson, Jr. et al.
patent: 4163291 (1979-07-01), Suzuki et al.
patent: 4236225 (1980-11-01), Jansen et al.
patent: 4258418 (1981-03-01), Heath
patent: 4270183 (1981-05-01), Robinson et al.
patent: 4271480 (1981-06-01), Vinot
patent: 4285038 (1981-08-01), Suzuki et al.
patent: 4342081 (1982-07-01), Dubuc
patent: 4433394 (1984-02-01), Torii et al.
patent: 4476542 (1984-10-01), Crean et al.
patent: 4486854 (1984-12-01), Yuni
patent: 4507760 (1985-03-01), Fraser
patent: 4521874 (1985-06-01), Rau et al.
patent: 4527233 (1985-07-01), Ambrosius, III et al.
patent: 4535427 (1985-08-01), Jiang
System Design/Memory Systems, Computer Design, Aug. 1, 1986, pp. 109-112, "FIFO RAM Controller Tackles Deep Data Buffering", by Tom Pai.
Data Sheet Entitled "FIFO RAM Controller" (Part Number 57/674219), Published by Monolithic Memories, Inc. in 1986.
"8257/8257--5 Progammable DMA Controller", Published by Intel Corporation, 1979, pp. 1-73 to 1-89.

Affiliated with

Also associated with

Rating

FIFO memory device including circuit for generating flag signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FIFO memory device including circuit for generating flag signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FIFO memory device including circuit for generating flag signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-442253