FIFO memory device

Static information storage and retrieval – Read/write circuit – Serial read/write

Patent

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Details

36518907, 365154, 365239, G11C 700

Patent

active

051576333

ABSTRACT:
An FIFO memory device which is used for digital communication devices and the like comprises a plurality of D-flip flops cascade-connected with each other for storing data; selectors connected between the D-flip flops for selecting an input data or a data to be stored which is outputted from the D-flip flop on the previous stage; and control circuits responsive to a clock signal, a write signal and a read signal for controlling the storing operation of the D-flip flops and the selection operation of the selectors. The control circuit stores a signal representative of presence or absence of data stored in the D-flip flops and performs control in such a manner that an input data is transferred to the D-flip flop on the final stage in which no data has been written for writing the data therein in response to a write signal and that data on respective D-flip flops are simultaneously shifted to the D-flip flop on the subsequent stage on every clock in response to a read signal.

REFERENCES:
patent: 3646526 (1972-02-01), Fagan et al.
patent: 4236225 (1980-11-01), Jansen et al.
patent: 4819201 (1989-04-01), Thomas et al.
patent: 4888741 (1989-12-01), Malinowski
patent: 5016221 (1991-05-01), Hamstra
patent: 5036489 (1991-07-01), Theobald
patent: 5046051 (1991-09-01), Doornhein et al.
Trade Model SN 745225 "Asynchronous FIFO Memory" by Texas Instrument Co., Ltd. pp. 6-34 through 6-41.

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