FIFO memory control circuit

Details FIFO memory control circuit FIFO memory control circuit

2001-03-08

2002-10-22

Elmore, Reba I. (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

In response to microinstruction

C711S109000, C711S110000

Reexamination Certificate

active

06470439

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a FIFO (First In First Out) memory control circuit for controlling FIFO memory which is used in various electronic devices. Specifically, the present invention relates to a FIFO memory control circuit capable of performing asynchronous read/write control when a write clock and a read clock are different and it is known or determined which of these clocks has a higher clock frequency.
2. Description of the Related Art
FIG. 11
shows a structure of a conventional FIFO memory control circuit
1100
. The FIFO memory control circuit
1100
includes a memory
101
, a write control section
102
, a read control section
103
, a write address circuit
104
, a read address circuit
105
, and a Full-Empty control circuit
106
.
The memory
101
is a dual-port RAM (Random Access Memory) in which reading and writing of data can be performed simultaneously, and which has a memory capacity of N words. In the memory
101
, while a write permission signal (WE) is asserted, data (WDATA) is written in an address designated by a write address (WADR) on a word-by-word basis at a clock timing of a write clock signal (WCLK). On the other hand, while a read permission signal (RE) is asserted, data (RDATA) is read from an address designated by a read address (RADR) on a word-by-word basis at a clock timing of a read clock signal (RCLK). The write permission signal (WE) is output from the write control section
102
(described later), and the read permission signal (RE) is output from the read control section
103
(described later).
The write address circuit
104
receives the write clock signal (WCLK) and the write permission signal (WE). While the write permission signal (WE) is asserted, the write address circuit
104
increments the write address (WADR) by one at a clock timing of the write clock signal (WCLK).
The read address circuit
105
receives the read clock signal (RCLK) and the read permission signal (RE). While the read permission signal (RE) is asserted, the read address circuit
105
increments the read address (RADR) by one at a clock timing of the read clock signal (RCLK).
The Full-Empty control circuit
106
is formed by an up-down counter
107
and a signal generator
108
. The Full-Empty control circuit
106
obtains the number of effective data, which is the difference between the number of data words written in the memory
101
and the number of data words read from the memory
101
. That is, the “number of effective data words” means the number of data words in the memory
101
which have not yet read therefrom. Based on the number of effective data, the Full-Empty control circuit
106
generates control signals for writing and reading operations.
The up-down counter
107
receives the write permission signal (WE) as a count-up enable signal (UPEN) which permits a count-up operation and the read permission signal (RE) as a count-down enable signal (DNEN) which permits a count-down operation. While one of the count-up enable signal (UPEN) and the count-down enable signal (DNEN) is asserted, the up-down counter
107
performs a count operation at a clock timing of the write clock signal (WCLK). A count value (CNT) of the up-down counter
107
is equal to the number of effective data words, which is output to the signal generator
108
.
The signal generator
108
receives the count value (CNT) from the up-down counter
107
. When the received count value (CNT) is 0, the signal generator
108
outputs to the read control section
103
an empty signal (EMP) which indicates that the memory
101
has no data to be read. When the received count value (CNT) is N (the number of words storable in the memory
101
), the signal generator
108
outputs to the write control section
102
a full signal (FLL) which indicates that the memory
101
has no more capacity to store data.
The write control section
102
receives the full signal (FLL). While the full signal (FLL) is asserted, the write control section
102
prohibits writing data in the memory
101
, thereby preventing the memory
101
from losing data due to overwriting.
The read control section
103
receives the empty signal (EMP). While the empty signal (EMP) is asserted, the read control section
103
prohibits reading data from the memory
101
, thereby preventing one data word from being read twice from the memory
101
.
FIG. 12
shows a structure of a conventional FIFO memory control circuit
1200
in which an up-down counter
107
′ performs a count operation at a clock timing of a read clock signal (RCLK). In other respects, the FIFO memory control circuit
1200
has the same structure as the conventional FIFO memory control circuit
1100
, and descriptions thereof are omitted.
In the conventional FIFO memory control circuit
1100
, when the write clock signal (WCLK) and the read clock signal (RCLK) have the same frequency, the up-down counter
107
uses the write permission signal (WE) as a count-up enable signal (UPEN) which permits a count-up operation and the read permission signal (RE) as a count-down enable signal (DNEN) which permits a count-down operation. While one of the count-up enable signal (UPEN) and the count-down enable signal (DNEN) is asserted, the up-down counter
107
performs a count operation at a clock timing of the write clock signal (WCLK). In the conventional FIFO memory control circuit
1200
, when the write clock signal (WCLK) and the read clock signal (RCLK) have the same frequency, the up-down counter
107
′ uses the write permission signal (WE) as a count-up enable signal (UPEN) which permits a count-up operation and the read permission signal (RE) as a count-down enable signal (DNEN) which permits a count-down operation. While one of the count-up enable signal (UPEN) and the count-down enable signal (DNEN) is asserted, the up-down counter
107
′ performs a count operation at a clock timing of the read clock signal (RCLK).
In these conventional FIFO memory control circuits
1100
and
1200
, when the write clock signal (WCLK) and the read clock signal (RCLK) have different frequencies, a count operation cannot be correctly performed.
For example, in the conventional FIFO memory control circuit
1100
shown in
FIG. 11
, the up-down counter
107
performs a count operation at a clock timing of the write clock signal (WCLK). In the case where the write clock signal (WCLK) has a higher frequency than that of the read clock signal (RCLK), as shown in
FIG. 13
, in one read cycle, the count-down enable signal (DNEN=RE) is asserted for a period longer than one cycle of the write clock signal (WCLK). In such a case, although only one data is actually read out, the count value of the up-down counter
107
may be decremented by 2 or more.
On the other hand, in the conventional FIFO memory control circuit
1200
shown in
FIG. 12
, the up-down counter
107
′ performs a count operation at a clock timing of the read clock signal (RCLK). In the case where the write clock signal (WCLK) has a higher frequency than that of the read clock signal (RCLK), as shown in
FIG. 14
, although data is actually written in, the count value of the up-down counter
107
′ may not be incremented.
Alternatively, when the read clock signal (RCLK) has a higher frequency than that of the write clock signal (WCLK), in the conventional FIFO memory control circuit
1100
shown in
FIG. 11
, although data is actually read out, the count value of the up-down counter
107
may not be decremented; in the conventional FIFO memory control circuit
1200
shown in
FIG. 12
, although only one data is actually written in, the count value of the up-down counter
107
′ may be incremented by 2 or more.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a FIFO memory control circuit includes: a write address circuit for generating a write address which is an operation address; a read address circuit for generating a read address which is another operation address; a memory which receives a writ

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