Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-01-04
2002-06-04
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S105000, C711S129000, C714S773000, C714S769000
Reexamination Certificate
active
06401168
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to improvements in data paths used in mass storage devices, or the like, and methods for implementing and operating same, and additionally to improvements in the construction and operation of a data FIFO between buffer manager and disk formatter circuitry of a controller circuit, or the like.
2. Relevant Background
In the operation of a controller circuit of a typical mass storage device, a buffer manager is provided to manage the flow of data between a host computer and a mass storage device, such as a hard rotating disk, or the like. As a part of its function, the buffer manager arbitrates between various competing demands for data bandwidth.
The buffer manager, which is typically controlled by a microprocessor provided in association with the controller circuit, is typically arranged to receive data from a host interface circuit, which, in turn, receives data from the host computer via a speed correcting FIFO memory. The buffer manager typically routes the data from the FIFO memory into the buffer memory. The buffer memories used in the past have typically been SRAM memory devices, but, recently DRAM memory devices have been used. The buffer memory may be separately provided, or may be provided as a part of the controller circuit of the mass storage device. The buffer manager, at an appropriate time, retrieves the data from the DRAM and writes it to the disk memory through a second FIFO memory.
The FIFO memories that are provided are generally needed to compensate for the differences in speed of the various circuitry through which the data must pass between the host computer and the mass storage device. For example, when the host computer writes data to the mass storage device, due to the amount of processing that must be performed on the data before it can be properly written to disk, or even to the data buffer in the controller circuit, the transfer of the data to or from the host computer would need to be moderated. The alternative is to slow the rate at which data is transferred from the host computer, which is undesirable. Consequently, two FIFO memories are provided, one between the host interface and the buffer manager and the other between the buffer manager and the disk formatter circuit.
In the past, the FIFO memories have been a fairly limited size, for example, of size sufficient to contain on the order of 32 or 64 words. The size of the FIFO memories is primarily determined by the rate at which data is transferred between the host computer and the mass storage device and the amount of delay that is required during the transfer.
An error correction code (ECC) device is also provided as a part of the controller circuit. The ECC device is operated in conjunction with the buffer manager to correct the data as it is being read from the mass storage device in a well known manner. (Typically the ECC device is not active during write operations to the disk, since no corrections via the ECC occur during disk writes.) However, in its operation, the ECC typically accesses the data through and under the control of the buffer manager.
Since one of the functions of the buffer manager is to arbitrate among the various devices contending for access to the data, the control of the data sought by the ECC device requires a significant amount of data bandwidth that otherwise could be available to the data in the data path between the computer and mass storage device. During the operation of the ECC device, the data on which the ECC device operates is held until the completion of the ECC functions on that data. At the conclusion of the error correction operations, the ECC circuit issues an “ECC done” signal to the buffer manager to release the data. Thus, it can be seen that if a large number of corrections are made by the ECC circuit to the data, which may be, for example, up to 30 random bytes per sector, the data bandwidth of the buffer manager may be significantly impacted. This ultimately results in slower data transfers between the host computer and the mass storage device.
What Is needed is an arrangement for use in a controller circuit of a mass storage device that does not have the data bottleneck caused by the operation of the buffer manager.
SUMMARY OF THE INVENTION
In light of the above, therefore, it is an object of the invention to provide an improved data path for mass storage devices, or the like.
It is another object of the invention to provide an improved architecture for mass data storage devices in which buffer bandwidth is not affected by ECC accesses, and in which ECC accesses can be completed more rapidly than most prior art devices.
It is another object of the invention to provide an improved architecture of the type described having an extended FIFO depth to which the ECC has access, and in which the ECC bandwidth is managed by circuitry associated with the FIFO before it goes to the buffer.
It is another object of the invention to provide an improved architecture of the type described in which the number of cycles required to complete an ECC correction are reduced from typical ECC cycles required in prior art devices.
It is an object of the invention to provide a method and apparatus to increase the buffer bandwidth of a disk controller, or the like.
It is another object of the invention to provide a capability for an ECC device to access data to be corrected faster than heretofore.
It is another object of the invention to provide an improved data path that enables DRAMs to be used, if desired, for controller circuit buffer memory.
It is yet another object of the invention to provide an improved data path that enables correct-on-the-fly ECC correction capabilities.
These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims.
In accordance with a broad aspect of the invention, a data storage device is provided. The data storage device has a data storage unit and a FIFO memory. The FIFO memory has at least sufficient memory capacity to contain three sectors of data associated with the data storage unit. An ECC unit has random access to any sector contained in the FIFO memory so that error correction and control is performed on data in the FIFO memory. A FIFO memory controller controls locations at which data is written into and read from the FIFO memory. With this arrangement, the FIFO memory may be a DRAM, a single-port RAM, an SRAM, a dual-port RAM, a two-port RAM, or other suitable memory type. The FIFO memory controller controls the locations at which data is written into and read from the FIFO memory so that as data is written into a first portion of the memory containing a sector currently being written, the ECC unit concurrently accesses a second portion of the memory containing a sector previously written to correct data therein, and data that has already been corrected by the ECC unit in a third portion of the memory is concurrently being read from the FIFO memory.
According to another broad aspect of the invention, a mass data storage device is provided that has a rotating disk memory having a number of sectors or containing data. A FIFO memory has three memory sections, each for containing an entire sector of data associated with respective sectors of the rotating disk memory. An ECC unit has random access to any data contained in the FIFO memory. The ECC unit Is operated to perform error correction on data while the data is contained in the FIFO memory. A FIFO memory controller controls locations at which data is written into and read from the FIFO memory, and locations at which data correction is performed by the ECC unit, so that as data is written into a first portion of the memory containing a sector currently being written, the ECC unit concurrently accesses a second portion of the memory containing a sector previously written to correct data therein, and data that has already been c
James Michael
Williams John W.
Anderson Matthew D.
Brady W. James
Kim Matthew
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
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