FIFO control circuit

Details FIFO control circuit FIFO control circuit

2007-05-15

2007-05-15

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C710S052000

Reexamination Certificate

active

10993671

ABSTRACT:
A FIFO control circuit for passing receive data and transmit data in a first-in first-out system, respectively, is provided. The FIFO control circuit comprises a receiving circuit; a transmitting circuit; a FIFO buffer for temporarily storing receive data received by the receiving circuit and transmit data to be transmitted by the transmitting circuit; a free space management circuit for managing free space of the FIFO buffer; a first address storage unit for storing an address range in which the receive data is stored in the FIFO buffer; a second address storage unit for storing an address range in which the transmit data is stored in the FIFO buffer; a write pointer control circuit writing the receive data and the transmit data; and a read pointer control circuit reading out the receive data and the transmit data from the FIFO buffer.

REFERENCES:
patent: 6269413 (2001-07-01), Sherlock
patent: 6339558 (2002-01-01), Ioki
patent: 6529951 (2003-03-01), Okuyama et al.
patent: 6643816 (2003-11-01), Uesugi et al.
patent: 6701390 (2004-03-01), Ehmann
patent: 2003/0210709 (2003-11-01), Inoue

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