FIFO circuit

Details FIFO circuit FIFO circuit

2000-04-06

2001-06-12

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S038000, C365S189120, C365S220000, C365S221000

Reexamination Certificate

active

06246257

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to FIFO circuits, and particularly relates to a FIFO circuit that serves as a data buffer to absorb data-speed changes between a data-supply side and a data-reception side.
BACKGROUND OF THE INVENTION
Conventionally, FIFO (first-in first-out) circuits are used as a buffer placed between a module for supplying data and a module for receiving data, and absorb data-speed changes between a data-supply side and a data-reception side, thereby achieving efficient data transmission.
A super scalar scheme is a technology that enhances performance of data processing units using FIFO circuits. This scheme achieves parallel processing of instructions. A FIFO circuit is used as a buffer that efficiently feeds instructions to a pipeline. In this configuration, the FIFO circuit is provided with extended ports in order to allow simultaneous access to a plurality of instructions to the extent commensurate with the degree of parallelism. A port is defined as a unit that permits simultaneous reading/writing of one memory cell.
In a data processing unit capable of simultaneous processing of four instructions, a FIFO circuit having four ports for data writing and four ports for data reading may be provided in an instruction fetch unit at a start of a pipeline. In this configuration, the FIFO circuit accumulates a stream of instructions that stalled at an instruction generation unit as they wait for available resources of the data processing unit, and serves to compensate for a gap created when an instruction cache fails to hit an instruction.
Japanese Patent Laid-open Application No.5-314758 discloses a FIFO circuit. This FIFO circuit includes a shift register that accumulates data received from a prior stage in synchronism with an input clock S
1
, a counter circuit that counts up in response to the input clock S
1
and counts down in response to an output clock, and an output selecting circuit that selects a stage of the shift register that corresponds to the count of the counter circuit and outputs an output of the selected stage.
This FIFO circuit has one input port and one output port. If a plurality of input ports and output ports are provided, a circuit configuration as shown in
FIG. 1
may be conceived.
FIG. 1
is a circuit diagram of a FIFO circuit used in the super scalar scheme. In the figure, DI
0
through DI
3
denote input ports. Instruction data coming to the input port are supplied to shift registers
10
through
13
, respectively. Here, the shift registers
10
through
13
have a two-stage configuration.
The first stage of the shift register
10
is connected to output ports D
0
through D
3
via respective tri-state buffers provided in a selector circuit
14
. The second stage is connected to the output port D
0
via one tri-state buffer. The first stage of the shift register
11
is connected to the output ports D
0
through D
3
via respective tri-state buffers provided in the selector circuit
14
. The second stage is connected to the output ports D
0
and D
1
via respective tri-state buffers.
The first stage of the shift register
12
is connected to the output ports D
0
through D
3
via respective tri-state buffers provided in the selector circuit
14
. The second stage is connected to the output ports D
0
, D
1
, and D
2
via respective tri-state buffers. The first and second stages of the shift register
13
are each connected to the output ports D
0
through D
3
via respective tri-state buffers provided in the selector circuit
14
.
A control circuit
15
controls valid data positions of the shift registers
10
through
13
. Further., the control circuit
15
generates control signals EF
0
through EF
3
and FF
0
through FF
3
in accordance with input-request-number signals (number of data items) SI
0
through SI
3
and output-request number signals (number of data items) SO
0
through SO
3
as well as in accordance with the valid data positions. The control signals are used for controlling the tri-state buffers in the selector circuit
14
, so that a number of data items, corresponding to the output-request number, are output from the output ports D
0
through D
3
. Here, data is output from the output port D
0
when the output-request number is 1 and data is output from the output ports D
0
and D
1
when the output-request number is 2. By the same token, the output ports D
0
through D
2
output data when the output-request number is 3.
In the FIFO circuit of the related art, the output port D
0
is connected to eight tri-state buffers of the selector circuit
14
, and the output port D
1
is connected to seven tri-state buffers of the selector circuit
14
. Further, the output port D
2
is connected to six tri-state buffers of the selector circuit
14
, and the output port D
3
is connected to five tri-state buffers of the selector circuit
14
.
The greater the number of tri-state buffers connected to an output port, the greater the load, thus preventing high-speed operation. In an integrated circuit, signal transmission is affected by using high and low levels of signal-line potential as signal information. A voltage difference V is achieved by accumulating (or discharging) charge Q on a signal line having a capacitance C. In this case, these parameters are related as:
Q=CV
  (1)
Charge Q is represented by an average electrical current Iave and time t as follows.
Q=Iavet
  (2)
From the equations (1) and (2), the following relation is obtained.
dt=CdV/Iave
  (3)
The equation (3) indicates that a time delay dt is related to a product of a parasitic capacitance C and a turn-on resistance of a transistor that is equal to a voltage difference dV divided by the average current Iave. Improvement in operational speed of integrated circuits has been attained by lowering the parasitic capacitance C via miniaturization of circuits, by lowering the voltage difference dV via use of a lower power voltage, and by increasing the average current Iave via use of low-resistance wiring material such as copper. The parasitic capacitance C is greatly affected by a technology used for manufacturing the integrated circuit and a structure of equal-voltage nodes. The larger the wires or the larger the number of connected transistors, the greater the parasitic capacitance C that needs to be charged or discharged.
As previously described, the FIFO circuit of the related art has a large number of tri-state buffers and thus a large number of transistors connected to each of the output ports D
0
through D
3
. As a result, it has a large parasitic capacitance C, which hinders high-speed operation.
Accordingly, the present invention is aimed at providing a FIFO circuit capable of high-speed operation by reducing the number of buffers connected to output ports and thereby lowering parasitic capacitance.
SUMMARY OF THE INVENTION
The invention is directed to a FIFO circuit having a plurality of input ports permitting parallel access thereto and a plurality of output ports.
The FIFO circuit has an input register which stores data supplied from the plurality of input ports. A shifter rearranges the data supplied from input register and a shift register stores and shifts the data supplied from the shifter. A selector circuit selects either the data supplied from the input register or the data supplied from the shift register such that valid data fill places of the output ports from a least significant side of the output ports. A control circuit manages the valid data of the input register and the shift register and controls the input register, shift register and selector circuit.
In this manner, the shifter rearranges the data supplied from the input register so as to shift the data inside the shift register. As a result, the present invention can reduce the number of buffers connecting the input register and the shift register to the plurality of output ports in the selector circuit, thereby lowering the parasitic capacitance of each output port so as to achieve high-speed operat

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