Fifo bus-sizing, bus-matching datapath architecture

Details Fifo bus-sizing, bus-matching datapath architecture Fifo bus-sizing, bus-matching datapath architecture

1999-09-17

2003-02-25

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S100000

Reexamination Certificate

active

06526470

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memories generally and, more particularly, to a bus-matching datapath architecture that may be used for bus-sizing and/or bus-matching in a memory such as a FIFO.
BACKGROUND OF THE INVENTION
Bus matching generally refers to matching the data width of one device, such as an 9-bit input data bus, with the data width of another device, such as a 18-bit memory array. Various combinations of bus matching, such as between 9-bit, 18-bit and 36-bit devices, and byte swapping are desirable.
Previous approaches implement a bus-matching and multiplexing block in series and before the datapath.
FIG. 1
illustrates such a conventional approach implemented for write-side multiplexing. Similar implementations are used for the read side.
Disadvantages with conventional approaches include the introduction of additional delays by the incorporation of one or more additional multiplexers in the datapath as well as an increased area for implementation the logic block.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising (i) one or more input paths, (ii) one or more output paths, and (iii) one or more switch circuits. The switch circuits may be configured to connect one or more of said input paths to one or more of said output data paths in response to one or more control signals. The present invention may be used to read and/or write data in one or more modes of operation such as 9-Bit Big Endian Write, 9-bit Little Endian Write, 18-bit Big Endian Write, 18-bit Little Endian Write, a 36-bit Write, 9-Bit Big Endian Read, 9-bit Little Endian Read, 18-bit Big Endian Read, 18-bit Little Endian Read, 36-bit Read or other modes.
The objects, features and advantages of the present invention include providing a circuit and method for implementing a bus-matching datapath architecture that may be used for bus-sizing in a memory such as a FIFO that is (i) faster than conventional approaches by reducing the delay path from a data input to a memory and/or (ii) less complex and uses less area than conventional approaches by implementing existing datapath multiplexing logic to also implement the bus-matching logic. The present invention does not incur any extra delay, and minimizes the required logic area by utilizing the existing logic that is used to multiplex data into the memory. The present invention may be applicable to any FIFO memory that requires bus-matching and/or bus-sizing capability. The present invention may also be used to ease back-end testing by allowing a test engineer to test the entire memory using a 9-bit channel for the data input/output rather than 36 bit channels.


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