FIFO buffer controller

Details FIFO buffer controller FIFO buffer controller

1987-10-15

1989-10-10

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Including signal comparison

365221, 36523002, 365236, G11C 700, G11C 800

Patent

active

048736678

ABSTRACT:
A FIFO (first in first out) control circuit for providing address information to a FIFO memory uses two up counters--one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two comparators along with a simple logic circuit provide two status output signals; namely full (or not) and empty (or not ).

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patent: 4616338 (1986-10-01), Helen et al.
patent: 4694426 (1987-09-01), Mason
Tunick, "Rich With Logic, Memory ICs Hone Their Specialties", Electronic Design, Jun. 11, 1987, pp. 77-86.
Pai, "FIFO RAM Controller Tackles Deep Data Buffering", Computer Design, Aug. 1, 1986, pp. 109-112.

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