Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-05
2004-07-13
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S303000, C257S505000, C257S513000, C257S514000
Reexamination Certificate
active
06762447
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to dynamic random access memories (DRAMS), and more particularly, to the use of field shield isolation in DRAMs.
BACKGROUND OF THE INVENTION
A particularly important integrated circuit device is the DRAM that comprises an array of memory cells arranged in rows and columns in a semiconductor body (chip, substrate) and word lines and bit lines over the surface of the chip to write in and read out bits stored in individual cells. Each memory cell generally includes a switch, typically an n-channel metal-oxide-semiconductor field effect transistor (MOSFET), in series with a storage capacitor.
In DRAM technology there is a continuing drive to increase the density of memory cells in the chip. This generally involves both a reduction in the size of individual memory cells and closer packing of the memory cells in the chip. The effect of the smaller memory cell size and closer memory cell packing results in undesirable problems with short and narrow channel effects in the transistor of the memory cell.
To meet these problems, it is the usual practice to increase the doping of a p-type well formed at the surface of the chip wherein are formed the n-channel MOSFETS that typically serve as the switches of the memory cells. However, the increase in p-type conductivity well doping tends to increase the junction leakage of the transistors. This degrades the retention time of the stored bits stored in the storage capacitor. This in turn requires more frequent refreshing of the stored information and this reduces the time during which the memory operates productively. Additionally, there is evidence that the increased electric field resulting in the semiconductor body resulting from the increase in p-type well doping electrically activates the silicon defects that are inherent in the silicon body (substrate). Still another problem that arises with closer packing is that the narrower shallow trenches needed for isolation tend to have a higher aspect ratio. This leads to increased silicon stress and greater concentration of silicon defects. These factors all tend to increase the array leakage that result in arrays with closer cell packing and smaller cell size.
Field-shield isolation was a popular isolation technique in the art of n-channel metal-oxide-semiconductor (NMOS) integrated circuits because it was relatively easy to implement when the standard technology for integrated circuits was pure NMOS technology that used only n-channel MOSFETS. However, NMOS technology has been largely supplanted by complementary MOS (CMOS) technology which uses both n-channel and p-channel MOSFETs to lower power dissipation. As a result of this technology shift, field-shield isolation in ICs was largely replaced by LOCOS (Local Oxidation of CMOS) and STI (Shallow Trench Isolation). This was because field-shield isolation is difficult to use with the CMOS technology since the n-channel and p-channel transistors require opposite polarity field-shield electrical bias, complicating the wiring of the mixed field-shield regions in the regions of complementary circuitry.
It is characteristic of DRAMS that, although they use n-channel and p-channel MOSFETS, the use of p-channel MOSFET (denoted as PMOS technology) is typically limited to the support circuitry that is used for addressing, sensing, and refreshing the memory cells and that this support circuitry is localized at the periphery of the chip. However, the main central area of the chip is used only for the array of memory cells that use only NMOS technology. Moreover, in those instances where PMOS is used instead for the transistors of the memory cells, the use of NMOS transistors is then generally limited to the support circuitry at the chip periphery.
In an article entitled “Effects of a New trench-isolated Transistor Using Sidewall Gates”, by Katsuhiko Hieda et al., IEEE Transaction on Electron Devices, Vol. 36, N. 9, September 1989, there is described the use of a trench formed in a semiconductor substrate. The trench is lined with a layer of silicon dioxide. Subsequently a lower portion of the trench is filed with polysilicon and an upper portion of the trench is filled with silicon dioxide. The polysilicon in the trench electrically floats in potential which can reduce the electrical isolation nominally provided by this type of trench isolation.
U.S. Pat. No. 5,557,135 (M. Hashimoto), issued Sep. 17, 1996, shows a type of field shield which uses a polysilicon filled trench which is dielectrically isolated from a substrate and is electrically connected via a top portion thereof to a voltage supply to electrically isolate n-channel FETS. The top connection increases the area of silicon needed and therefore undesirably increases the cost of the resulting chip. The extension of the polysilicon to the top of the trench increases capacitances of the memory cell.
SUMMARY OF THE INVENTION
The present invention exploits this characteristic of DRAMs that the central area where the memory cells are localized generally uses only one of NMOS or PMOS technology, rather than CMOS technology. Moreover, when the transistors are n-channel MOSFETs, they are typically formed in a p-type conductivity well. When the transistors are p-channel MOSFETs, they are then formed in a n-type conductivity well. Typically the top portion of the well is of a conductivity lower than the deep portion of the well.
The present invention uses for cell isolation a combination of the prior art silicon oxide shallow trench isolation (STI) and prior art doped-polysilicon field-shield isolation in which the doped field-shield polysilicon underlies the silicon oxide in the trench and is used to isolate the deeper part of well. Accordingly, the silicon oxide portion of the STI can be shallower that in the prior art technology. Moreover, the isolation provided by the doped polysilicon is made active, rather than passive, because it is maintained at an appropriate bias by being conductively connected to the monocrystalline silicon in the well, which is doped to be of like conductivity-type, and so can be more effective than the silicon oxide of the standard STI. Moreover, because the deeper portion of the isolation trench is filled with doped polysilicon, a lessor depth of silicon oxide needs to be deposited. This facilitates the filling of isolation trenches with high aspect ratios. Moreover, the doped polysilicon in the isolation trench provides a better thermal match to the surrounding monocrystalline silicon than does silicon oxide. This should reduce the number of silicon defects induced in the monocrystalline silicon, with a consequent reduction in the accompanying leakage. The height of the doped polysilicon in the isolation trench advantageously should be such as not to extend upwards enough to overlap bit-line diffusions near the chip surface so that bit-line capacitance due to the polysilicon shield can be negligible. The field shield is maintained at the potential of the deeper, generally more conductive, portion of the well, this forcing the potential of the nearby well silicon surfaces to produce active isolation.
Viewed from an apparatus aspect, the present invention is directed to a semiconductor body containing a semiconductor structure. The semiconductor body defines an isolation trench having sidewalls and upper and lower portions, and encircling an area of the semiconductor body which contains a semiconductor structure which is to be electrically isolated from other semiconductor structures contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is at least partly filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench being filled with a second electrical insulator.
Viewed from an other appara
Divakaruni Rama
Gruening Ulrike
LaRosa Giuseppe
Mandelman Jack A.
Radens Carl
Infineon Technologies North America Corp.
Lerner David Littenberg Krumholz & Mentlik LLP
Nguyen DiLinh
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