Field shield isolation structure for semiconductor memory device

Details Field shield isolation structure for semiconductor memory device Field shield isolation structure for semiconductor memory device

1990-11-19

1993-07-06

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257488, 257491, H01L 2702, H01L 2968, H01L 2978

Patent

active

052257045

ABSTRACT:
In a DRAM having stacked capacitor cells, elements are isolated by field shield isolating structure. The field shield isolating structure is formed surrounding both X and Y directions of the memory cell in the DRAM. The field shield isolating structure comprises an isolating electrode layer formed on a semiconductor substrate between adjacent memory cells with an insulating film interposed therebetween. Two impurity regions included in the adjacent memory cells and the isolating electrode layer constitute a MOS transistor. A voltage for maintaining the MOS transistor normally-off is applied to the isolating electrode layer. A portion of the stacked capacitor extends to the isolating electrode layer. One of the source/drain regions of the MOS transistor is formed in self-alignment, using a sidewall spacer formed of an insulating film on a sidewall of the field shield electrode as a mask.

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"Self-Aligned Field Shield Process", Dennard et al., Technical Disclosure Bulletin, vol. 16, No. 2, Jul. 1974, pp. 507-508.
"Shielded Silicon Gate Complementary MOS Integrated Circuit", IEEE Transactions on Electron Devices, Lin, et al., IEEE Transactions on Electron Devices, vol. ED-19, No. 11, Nov. 1972, pp. 1190-1207.

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