Field reconfigurable logic/memory array

Details Field reconfigurable logic/memory array Field reconfigurable logic/memory array

1995-01-31

1996-07-02

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Flip-flop

326 38, G11C 1100

Patent

active

055329578

ABSTRACT:
All of the components of a standard logic gate wherein high precision is required, preferably a NAND gate, are provided, preferably in bulk silicon and the remaining components required for a memory cell wherein relatively low precision is required, preferably an SRAM, as well as a mode select circuit are provided, preferably in a polysilicon layer over the bulk silicon. The mode select circuit is design to operate in plural modes, a two mode mode select circuit being the preferred embodiment. In any mode of operation as determined by the mode select circuit, all unused or unrequired circuitry is either isolated from the active portion of the circuit or used to enhance operation of required circuitry, such as, for example, operating in parallel therewith or in series therewith. The polysilicon layer, if used, can be disposed over the bulk silicon with vias and interconnects therebetween. The resulting circuit can require less circuit area required by a similar prior art circuits of both of the configurations obtainable, yet be capable of providing any one of plural selected functions. In addition, the improved hardware utilization is conducive to speed enhancement and lower power utilization due to paralleling.

REFERENCES:
patent: 4233524 (1980-11-01), Burdick
patent: 4975601 (1990-12-01), Steele
patent: 5001368 (1991-03-01), Cliff
patent: 5012135 (1991-04-01), Kaplinsky
patent: 5146117 (1992-09-01), Larson

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