Field programmable memory array

Details Field programmable memory array Field programmable memory array

2000-02-22

2001-05-15

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S220000, C365S230060

Reexamination Certificate

active

06233191

ABSTRACT:

TECHNICAL FIELD
This invention relates to data memory and more specifically to a programmable memory array with associated programmable routing and control resources. This invention also relates to a programmable memory array incorporated together with a field programmable gate array.
BACKGROUND OF THE INVENTION
Known integrated memory arrays generally have a fixed depth and fixed width as associated with a given data storage application. Accordingly, different data storage applications may require separate respective memory arrays for meeting the different depth/width requirements. However, it would be advantageous if a single memory resource were capable of meeting the different depth/width application needs.
A variety of known memory devices are available for providing different memory access techniques. The most common memory access technique includes simple addressable read/write memory functionality. Other access techniques include LIFO (Last In First Out), FIFO (First In First Out) and rollover data stack operations. Existing data storage devices are generally tailored to specific, fixed access techniques. However, it would be advantageous if a memory device were programmable to selectively provide combinations of access techniques.
Programmable integrated circuits are known in the art and include programmable gate arrays (PGA) which provide an array of distinct, uncommitted logic cells. A programmable interconnect network is usually provided for interconnecting the cells and/or to provide data input to and output from the array. Customization or programming of the otherwise generally designed logic cells and interconnect network is performed for implementing a particular application. One such device is a field-programmable gate array (FPGA), wherein the configuration of the FPGA can be performed by a user “in the field.” The configuration of the FPGA is effected by using electrically programmable fusible links, anti-fuses, memory controlled transistors or floating gate transistors. To program the FPGA, configuration data is transferred from an external memory device to electrically programmable resources of the FPGA. As densities of these field programmable gate arrays increase, the demand for on-board memory/storage functionality likewise increases. Accordingly, it would be desirable to provide an integrated circuit including an FPGA together with a programmable memory array, which memory array could be capable of implementing various configurations, and/or provide one of a variety of memory access techniques.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved memory array.
It is a another object of the present invention to provide a programmable memory array that is programmably configurable for providing a variety of data storage architectures.
It is a further object of the present invention to provide a memory array selectively programmable for implementing a variety of memory access techniques.
It is yet a further object of the present invention to provide an integrated circuit incorporating a field programmable gate array together with a programmable memory array.
It is yet a further object of the present invention to provide an integrated circuit incorporating a field programmable gate array together with a field programmable memory array, wherein the field programmable memory array is accessible during configuration of the field programmable gate array, during reconfiguration of the field programmable gate array, or during normal functionality of the field programmable gate array.
The present invention is, in one aspect, a field programmable memory array having a plurality of memory sub-arrays. The memory sub-arrays are selectively programmable for implementing a variety of different memory configurations and operating modes. In general, each sub-array can be programmed into, and thereafter accessed using, one of a set of modes. The set of modes includes, in one embodiment, wide RAM, deep RAM, FIFO and LIFO.
Numerous programmable structures are provided by the present invention to effect the programming of the portions of the memory array. For example, the array may include an address decoder and a programmable access unit for providing read and write input addresses to the address decoder during associated read and write operations of the memory array. The programmable access unit may further comprise a first address counter, a first clock control unit and an address comparison unit.
The bit lines of the memory array are placed into a programmable, hierarchical arrangement. Local bit lines, semi-global bit lines and global bit lines can be provided and are programmably interconnectable to provide a high degree of bit line programmability. Further, the interconnected bit line structure is programmably connectable to I/O buses.
A primary I/O bus and a secondary I/O bus can be provided, along with first and second selective couplers for programmable connections thereto.
A programmable address decoder may be provided having M word lines, a plurality of address lines propagating address data, and a decoder circuit for selectively driving a given word line of the M word lines as selected in accordance with address data of the plurality of address lines. A selective coupler can also be provided having a plurality of inputs coupled to an associated set of lines of an address bus, and an output coupled to an address line of the plurality of address lines, the selective coupler selectively coupling its output to one of its plurality of inputs in accordance with programming data.
A selective read capture latch can be provided for selectively interfacing to the hierarchical bit line structure. The selective read capture latch may include at least first and second hierarchy inputs, a memory unit having an input and an output, and selective coupling means between the first and second hierarchy inputs and the input of the memory unit, for selectively coupling one of the first and second hierarchy inputs to the input of the memory unit for propagating data therebetween in accordance with an associated hierarchy read capture clock. Precharge means may be provided for pre-charging at least one bit line of the hierarchical bit line structure.
In alternate embodiments, programmable transfer paths and scan chain latches can be provided between the memory cells of the array to provide a physical LIFO/FIFO function, as well as provide testability for the cells and related paths in the array, respectively.
In a preferred embodiment, the field programmable memory array (FPMA) disclosed herein can be integrated with the programmable logic cells of a field programmable gate array (FPGA) to provide a fully programmable logic system which includes highly programmable combinational and memory circuitry.
The aforementioned, along with numerous other features of the present invention, disclosed below, provide a significant improvement over prior art memory systems wherein the memory access technique was fixed, offering little or no flexibility for user access thereto.


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