Field programmable logic arrays with transistors with...

Details Field programmable logic arrays with transistors with... Field programmable logic arrays with transistors with...

2002-06-28

2003-01-28

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185260

Reexamination Certificate

active

06512695

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits and in particular to field programmable logic arrays with transistors with vertical gates.
BACKGROUND OF THE INVENTION
Logic circuits are an integral part of digital systems, such as computers. These devices present a problem to integrated circuit manufacturers, who cannot afford to make integrated logic circuits perfectly tailored to the specific needs of every customer. Instead, general purpose very large scale integration (VLSI) circuits are defined. VLSI circuits serve as many logic roles as possible, which helps to consolidate desired logic functions. However, random logic circuits are still required to tie the various elements of a digital system together.
Several schemes are used to implement these random logic circuits. One solution is standard logic, such as transistor-transistor logic (TTL). TTL integrated circuits are versatile because they integrate only a relatively small number of commonly used logic functions. The drawback is that large numbers of TTL integrated circuits are typically required for a specific application. This increases the consumption of power and board space, and drives up the overall cost of the digital system.
Other alternatives include fully custom logic integrated circuits and semi-custom logic integrated circuits, such as gate arrays. Custom logic circuits are precisely tailored to the needs of a specific application. This allows the implementation of specific circuit architectures that dramatically reduces the number of parts required for a system. However, custom logic devices require significantly greater engineering time and effort, which increases the cost to develop these circuits and may also delay the production of the end system.
Semi-custom gate arrays are less expensive to develop and offer faster turnaround because the circuits are typically identical except for a few final-stage steps, which are customized according to the system design specifically. However, semi-custom gate arrays are less dense, so that it takes more gate array circuits than custom circuits to implement a given amount of random logic.
Between the extremes of general purpose devices on the one hand and custom and semi-custom gate arrays on the other, are programmable logic arrays (PLAs). PLAs which are programmable out in the field are known as field programmable logic arrays (FPLAs). FPLAs provide a more flexible architecture via user-programmed on-chip fuses or switches to perform specific functions for a given application. FPLAs can be purchased “off the shelf” like standard logic gates and are custom tailored like gate arrays in a matter of minutes.
To use FPLAs, system designers draft equations describing how the hardware is to perform, and enter the equations into a FPLA programming machine. The unprogrammed FPLAs are inserted into the machine, which interprets the equations and provides appropriate signals to the device to program the FPLA which will perform the desired logic function in the user's system.
Recently, FPLAs based on erasable-programmable-read-only memory cells (EPROMs) fabricated with CMOS (complimentary-metal-oxide-semiconductor) technology have been introduced. Such devices employ floating gate transistors as the FPLA switches, which are programmed by hot electron effects. The EPROM cells are erased by exposure to ultraviolet light or other means. EEPROMs (Electrically Erasable Programmable Read Only Memory) can be erased and programmed while in circuit using Fowler-Nordheim tunneling. However, a disadvantage of current EEPROMs is that they have a large cell size and require two transistors per cell. Herein is where one of the problem lies.
Technological advances have permitted semiconductor integrated circuits to comprise significantly more circuit elements in a given silicon area. To achieve higher population capacities, circuit designers strive to reduce the size of the individual circuit elements to maximize available die real estate. FPLAs are no different than the other circuit elements in that denser circuits are required to support these technological advances.
Another important problem with EEPROM, EAPROM (electrically alterable programmable read only memory), and flash memory devices is the adverse capacitance ratio between the control gate and the floating gate. That is, the capacitance between the control gate to floating gate (CCG) is about the same as the floating gate to substrate capacitance (CFG).
FIG. 1A
is a block diagram of a horizontal EEPROM, EAPROM, or flash memory device formed according to the teachings of the prior art. As shown in
FIG. 1A
, conventional horizontal floating gate transistor structure
101
includes a source region
110
and a drain region
112
separated by a channel region
106
in a horizontal substrate
100
. A floating gate
104
is separated by a thin tunnel gate oxide
105
shown with a thickness (t
1
). A control gate
102
is separated from the floating gate
104
by an intergate dielectric
103
shown with a thickness (t
2
). Such conventional devices must by necessity have a control gate
102
and a floating gate
104
which are about the same size in width.
FIG. 1B
is a block diagram of a vertical EEPROM, EAPROM, or flash memory device formed according to the disclosure in a co-pending, commonly assigned application by W. Noble and L. Forbes, entitled “Field programmable logic array with vertical transistors,” Ser. No. 09/032,617, filed Feb. 27, 1998.
FIG. 1B
illustrates that vertical floating gate transistor structures have a stacked source region
110
and drain region
112
separated by a vertical channel region
106
. The vertical floating gate transistor shown in
FIG. 1B
further includes a vertical floating gate
104
separated by a thin tunnel gate oxide
105
from the channel region
106
. A vertical control gate
102
is separated from the floating gate
104
by an intergate dielectric
103
. As shown in
FIG. 1B
, the vertical control gate
102
and the vertical floating gate
104
are likewise about the same size in width relative to the channel region
106
.
Conventionally, the insulator, or intergate dielectric,
103
between the control gate
102
and the floating gate
104
is thicker (t
2
) than the gate oxide
105
(t
1
) to avoid tunnel current between the gates. The insulator, or intergate dielectric,
103
is also generally made of a higher dielectric constant insulator
103
, such as silicon nitride or silicon oxynitride. This greater insulator thickness (t
2
) tends to reduce capacitance. The higher dielectric constant insulator
103
, on the other hand, increases capacitance. As shown in
FIG. 1C
, the net result is that the capacitance between the control gate and the floating gate (CCG) is about the same as the gate capacitance of the thinner gate tunneling oxide
105
between the floating gate and the substrate (CFG). This undesirably results in large control gate voltages being required for tunneling, since the floating gate potential will be only about one half that applied to the control gate.
As design rules and feature size (F) in floating gate transistors continue to shrink, the available chip surface space in which to fabricate the floating gate also is reduced. In order to achieve a higher capacitance between the control gate and floating gate (CCG) some devices have used even higher dielectric constant insulators between the control gate and floating gate. Unfortunately, using such higher dielectric constant insulators involves added costs and complexity to the fabrication process.
Therefore, there is a need in the art to provide field programmable logic arrays which can operate with lower control gate voltages and which do not increase the costs or complexity of the fabrication process. Further such devices should desirably be able to scale with shrinking design rules and feature sizes in order to provide even higher density integrated circuits.
SUMMARY OF THE INVENTION
The above mentioned problems with field programmable logic arrays (PLA's)

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