Field programmable gate array with mask programmed analog functi

Details Field programmable gate array with mask programmed analog functi Field programmable gate array with mask programmed analog functi

1997-01-31

1998-10-13

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, H03K 19177

Patent

active

058217762

ABSTRACT:
A mixed signal integrated circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed analog function circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the analog function circuits, and one of the input/output pads of the first group is connected to an output of one of the analog function circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input/output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input/output pads, and inputs and outputs of the analog function circuits from the mask programmable analog portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections of selected ones the first and second segments, intersections of inputs and outputs of the digital logic function modules and selected interconnect conductors, intersections of the first group of input/output pads and selected ones of the interconnect conductors, intersections with outputs of the analog function circuits and selected ones of the interconnect conductors, and intersections with the inputs of the analog function circuits and selected ones of the interconnect conductors.

REFERENCES:
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 5068603 (1991-11-01), Mahoney
patent: 5107146 (1992-04-01), El-Ayat
patent: 5191242 (1993-03-01), Agrawal et al.
patent: 5329181 (1994-07-01), Ridgeway
patent: 5493239 (1996-02-01), Zlotnick
patent: 5543730 (1996-08-01), Cliff et al.
patent: 5548228 (1996-08-01), Madurawe
patent: 5548552 (1996-08-01), Madurawe
patent: 5550839 (1996-08-01), Buch et al.
patent: 5559447 (1996-09-01), Rees
patent: 5559465 (1996-09-01), Shah
patent: 5563528 (1996-10-01), Diba et al.
patent: 5563592 (1996-10-01), Cliff et al.
patent: 5568081 (1996-10-01), Lui et al.
patent: 5581198 (1996-12-01), Trimberger
patent: 5583749 (1996-12-01), Tredennick et al.
patent: 5590305 (1996-12-01), Terrill et al.
patent: 5598108 (1997-01-01), Pedersen
patent: 5600597 (1997-02-01), Kean et al.
patent: 5625301 (1997-04-01), Plants et al.
patent: 5631577 (1997-05-01), Freidin et al.
patent: 5633830 (1997-05-01), Sung et al.
patent: 5635851 (1997-06-01), Tavana
patent: 5640106 (1997-06-01), Erickson et al.
patent: 5640308 (1997-06-01), Osann, Jr. et al.
patent: 5642058 (1997-06-01), Trimberger et al.
patent: 5642262 (1997-06-01), Terrill et al.
patent: 5644496 (1997-07-01), Agrawal et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5650734 (1997-07-01), Chu et al.
patent: 5652529 (1997-07-01), Gould et al.
patent: 5652904 (1997-07-01), Trimberger
patent: 5654564 (1997-08-01), Mohsen
patent: 5654649 (1997-08-01), Chua
patent: 5661409 (1997-08-01), Mohsen
patent: 5661685 (1997-08-01), Lee et al.
patent: 5671234 (1997-09-01), Philips et al.
patent: 5671432 (1997-09-01), Bertolet et al.
patent: 5677691 (1997-10-01), Hosticks et al.
patent: 5680061 (1997-10-01), Veenstra et al.
patent: 5682106 (1997-10-01), Cox et al.
Brown, Chappell, "Data-flow Architecture Runs on FPGA", Nov. 4, 1996, EE Times, Issue 926, pp. 41-42.
Bursky Dave, "Programmable Arrays Mix FPGA and ASIC Blocks", Oct. 14, 1996, Electronic Design, pp. 69-74.
Cypress, "Getting to Grips FPGAs", Aug. 1996, Australian Electronics Engineering, pp. 46, 48.
Fawcett et al., "Reconfigurable Processing with Field Programmable Gate Arrays", 1996 IEEE, International Conference on Applications-Specific Systems, Architecture and Processors, pp. 293-302.
Ristelhueber, Robert, "A Marriage of Convenience--Integration of PLDs and ASICs promises big gains, risks for chip vendors", Jan. 1997, Electronic Business Today, pp. 63-64.
Tchoumatchenko, et al., "FPGA Design Migration: Some Remarks", Sep. 23-25, 1996, 6th International Workshop on Field-Programmable Logic and Applications, FPL '96, Darmstadt, Germany, Proceedings, pp. 405-409.
Wilson, Ron, "Actel Unveils FPGA Family", Oct. 28, 1996, Electronic Engineering Times, Issue 925, pp. 88, 92.
Won, Martin S.,et al., "Building FIR Filters in Programmable Logic", Aug. 1996, Embedded Systems Programming, pp. 48-50, 52, 54, 56, 58-59.

Affiliated with

Also associated with

Rating

Field programmable gate array with mask programmed analog functi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Field programmable gate array with mask programmed analog functi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field programmable gate array with mask programmed analog functi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-316521