Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-06-07
2001-06-05
Wamsley, Patrick (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S040000, C326S041000
Reexamination Certificate
active
06242945
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a field programmable gate array (FPGA) architecture. More specifically, the present invention relates an FPGA which includes a dedicated gate array functionality.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a portion of a conventional FPGA
100
. The FPGA
100
typically includes a two dimensional array of configurable logic blocks (CLBs), which includes CLBs
101
A-
101
I as illustrated. Each of these CLBs
101
A-
101
I includes a block of configurable logic elements (CLEs) and corresponding programmable routing resources. For example, CLB
101
A includes CLE
102
and routing resources
103
. The routing resources associated with the various CLBs can be programmed by the user to provide various connections among the CLEs. In addition, the user can program the CLEs to implement different functions.
The flexibility provided by CLBs
101
A-
101
I comes at the cost of logic density. For example, suppose that the CLBs
101
A-
101
E are configured to implement an adder function having a certain number of bits. The CLBs required to implement such an adder function will have a larger layout area than a dedicated adder function having the same number of bits. FPGA
100
exhibits a reduced logic density with respect to dedicated circuits because of the additional resources required to make the routing resources and the CLEs programmable.
As an alternative to FPGAs, non-field programmable gate arrays can be programmed to implement application specific functions. The function of a non-field programmable gate array is defined during the later stages of manufacture, after a defined pattern of transistors has been formed. (A field programmable gate array, as its name implies, is programmed by the user.) An example of a non-field programmable gate array is a sea-of-gates (SOG) gate array, which is a mask programmed gate array.
An SOG gate array, in which a pattern of transistors are interconnected by custom patterns of metal lines, has a significantly higher logic density than the CLBs
101
A-
101
I of FPGA
100
. In an SOG gate array, a predefined pattern of transistors are connected directly with user-defined metal, both to form gates and to interconnect those gates. Consequently, the extensive programmable routing resources required for FPGA
100
are not present in an SOG gate array. However, non-field programmable gate arrays, such as SOG gate arrays, are inflexible in that they do not provide for field programmability.
FPGAs and non-field programmable gate arrays have been combined in a single device as set forth by Tavana et al. in U.S. Pat. No. 5,825,202 issued Oct. 20, 1998. However, this patent describes an FPGA portion of the device which is located within one dedicated region, and a non-field programmable gate array portion of the device which is located within a separate dedicated region. These dedicated regions are laterally separated, such that a common boundary separates the FPGA portion from the non-field programmable gate array portion. As a result of this layout, all interconnections between the FPGA portion and the non-field programmable gate array portion must cross the common boundary. This requirement can result in interconnect congestion, which in turn, can result in interconnect routing limitations.
It would therefore be desirable to have an FPGA which exhibits the field programmability of a conventional FPGA, as well as the improved logic density of a non-field programmable gate array, without exhibiting excessive congestion within the interconnect structure.
SUMMARY
Accordingly, the present invention provides an FPGA having a plurality of CLBs. Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array, such as a mask programmed gate array, or more specifically, a sea-of-gates (SOG) gate array. Each of the non-field programmable gate arrays is relatively small in silicon area. However, the non-field programmable gate arrays in the various CLBs can be connected (via user-defined metal interconnects) to form one or more relatively large non-field programmable gate array circuits which are distributed throughout the FPGA. In one example, each of the non-field programmable gate arrays can include on the order of 100 gates. The logic density provided by the non-field programmable gate arrays (which is much greater than the logic density of the CLE circuits), can increase the logic density of the FPGA approximately five-fold in one embodiment of the invention.
The programmable interconnect resources include a plurality of interconnect segments and programmable switch points. The programmable switch points are programmable to selectively couple the interconnect segments, the CLE circuits and the non-field programmable gate arrays. The following configurations can be implemented by appropriately programming the programmable switch points: (1) the interconnect segments can provide signals to the CLE circuit and/or the non-field programmable gate array; (2) the non-field programmable gate array can provide signals to the CLE circuit or the interconnect segments; and (3) the CLE circuit can provide signals to the interconnect segments and/or the non-field programmable gate array. A large degree of interconnection flexibility is therefore available within the FPGA.
Because each of the CLBs includes a non-field programmable gate array, the non-field programmable gate array functionality is effectively distributed over the entire FPGA. Moreover, because each of the CLBs includes a non-field programmable gate array, each of the CLE circuits is readily connectable to a non-field programmable gate array.
The present invention will be more fully understood in view of the following detailed description taken together with the drawings.
REFERENCES:
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5296759 (1994-03-01), Sutherland et al.
patent: 5640327 (1997-06-01), Ting
patent: 5649219 (1997-07-01), Matsushima
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5959466 (1999-09-01), McGowan
patent: 6094066 (2000-07-01), Mavis
patent: 6150837 (2000-11-01), Beal et al.
patent: 57055625 (1982-04-01), None
patent: WO 95/16993 (1995-06-01), None
patent: WO 98/38741 (1998-09-01), None
Barbara Tuck, “Low Power, Density, and Better Tools Propel Cell-Based ASICs”, Computer Design, vol. 35, No. 13, Dec. 1996, pp. 79-80, 82, 84, 86, 88-89.
IBM, “Mixture of Field and Factory Programmed Logic Cells in a Single Device”, IBM Technical Disclosure Bulletin, vol. 38, No. 4, Apr. 1995, pp. 499.
“The Programmable Logic Data Book”, 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 4-1 through 4-45.
Hoffman, Esq. E. Eric
Tan Vibol
Wamsley Patrick
Xilinx , Inc.
Young Edel M.
LandOfFree
Field programmable gate array with mask programmable I/O... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Field programmable gate array with mask programmable I/O..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field programmable gate array with mask programmable I/O... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2540883