Field programmable gate array with high speed SRAM based configu

Details Field programmable gate array with high speed SRAM based configu Field programmable gate array with high speed SRAM based configu

1997-11-18

2000-02-22

Sheikh, Ayaz R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

34082583, 326 39, G06F 1200

Patent

active

060292369

ABSTRACT:
A field programmable gate array (FPGA) comprising a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM is disclosed. In accordance with the present invention, each configurable function block includes a volatile logic array comprised of an array of "AND" gates and an array of "OR" gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are then capable of serving the user of the FPGA in two modes of operation. In a first mode of operation, logic mode, the SRAM cells provide for the programmable connections which direct the logic operations in the volatile logic array. In a second mode of operation, memory mode, the SRAM cells function as a block of SRAM which can then be written to, and read from, using standard SRAM access signals.

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