Field programmable gate array with distributed gate-array functi

Details Field programmable gate array with distributed gate-array functi Field programmable gate array with distributed gate-array functi

1997-03-04

1999-02-23

Tokar, Michael J.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 326 40, 326 41, H03K 19177

Patent

active

058748342

ABSTRACT:
A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable interconnect resources are programmed to selectively couple or decouple each CLE circuit from its corresponding non-field programmable gate array. Dedicated interconnect resources enable adjacent non-field programmable gate arrays to be coupled. By coupling adjacent non-field programmable gate arrays, one or more relatively large nonfield programmable gate arrays can be formed. The non-field programmable gate arrays have a greater logic density than the CLE circuits, thereby providing an improved logic density to the CLBs. Moveover, because each CLB includes a non-field programmable gate array, each of the CLE circuits is readily connectable to a non-field programmable gate array. The non-field programmable gate array can be used to provide a plurality of mask-programmable input/output driver circuits for connection to the pads of the FPGA.

REFERENCES:
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5296759 (1994-03-01), Sutherland
Xilinx, Inc., "The Programmable Logic Data Book" 1996, pp. 4-1 through 4-45.
Tuck, B., "Low Power, Density, and Better Tools Propel Cell-Based ASICs", Computer Design, vol. 35, No. 13, Dec. 1996, pp. 79-80, 82, 84, 86,88-89.
IBM, "Mixture of Field and Factory Programmed Locic Cells in a Single Device", IBM Technical Disclosure Bulletin, vol. 38, No. 4, Apr. 1995, p. 449.

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