Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1994-07-29
1995-06-20
Westin, Edward P.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 38, G06F 738, H03K 19173
Patent
active
054263794
ABSTRACT:
A programmable gate array comprises an array of configurable logic blocks. Each configurable logic block is controlled by one or more rows and columns of memory cells in a memory array. According to the invention, an older bitstream may be used without modification in a newer programmable gate array. A frame register includes a plurality of active memory locations called frame bits which correspond to columns of memory cells within the memory array and at least one spare frame bit which does not correspond to a column of memory cells within the memory array. A similar configuration of row pointer cells comprises a shift register for enabling row by row addressing of the memory array. Spare frame bits and spare pointer cells are selectively either loaded or bypassed by programmable selector circuits, permitting expansion of the memory array in future programmable gate arrays, and thereby allowing additional functionality to be added to later versions of the programmable gate array without requiring designers of gate array applications to modify bitstreams which they previously designed.
REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4855954 (1989-08-01), Turner et al.
patent: 4940909 (1990-07-01), Mulder et al.
Xilinx Programmable Gate Array Data Book, 1994, available from Xilinx, Inc., 2100 Logic Dr., San Jose, Calif. 95124.
Calogero Stephen
Ferrell John S.
Westin Edward P.
Xilinx , Inc.
Young Edel M.
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