Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1994-04-01
1995-09-26
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 39, 326 21, H03K 1900
Patent
active
054537061
ABSTRACT:
A circuit and method in a field programmable gate array (FPGA) for eliminating programming contentions which occur during array configuration comprises a switching matrix of crossing lines, in which cross points, called programmable interconnection points (PIPs), are connected by configuration transistors. The configuration transistors can be programmed to connect the lines at the PIPs or to leave the lines unconnected. Output drivers are selectively connected by the PIPs to the signal lines. Prior to the configuration and reconfiguration of the FPGA, drivers to the gate array are disabled to prevent potentially catastrophic driver contention. The contention eliminating circuit of the present invention holds the logical values of the output buffers to a single logic level until programming has been completed. The circuit of the preferred embodiment comprises a two input AND gate which combines the incoming data signals with a gating signal. The first set of AND gate inputs receives and transmits the incoming data used for driving the input buffers. The second set of inputs to the AND gates receives enable signals which control the propagation of the input data to the PIP array until programming of the PIPs is completed.
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Santamauro Jon
Westin Edward P.
Xilinx , Inc.
Young Edel M.
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