Field programmable gate array having programming instructions in

Details Field programmable gate array having programming instructions in Field programmable gate array having programming instructions in

1997-08-29

1999-04-06

An, Meng-Ai T.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 364489, G06F 1300

Patent

active

058929614

ABSTRACT:
A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes the programming instructions to efficiently load configuration data into the configuration memory array. For instance, configuration data can be temporarily stored in the CPU and reused where data patterns in the configuration memory array repeat. Use of the programmable CPU for loading the configuration memory array reduces the amount of data transmitted to the FPGA during array configuration.

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"The Programmable Logic Data Book" copyright 1994, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 2-105 to 2-132.

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