Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1997-10-15
2001-04-10
Wiley, David A (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C326S034000
Reexamination Certificate
active
06216191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and, in particular, to high-density programmable logic devices, such as field programmable gate arrays.
2. Description of the Related Art
Most high-density field programmable gate arrays (FPGAs) reside in systems that have a host processor, such as a microprocessor, microcontroller, digital signal processor, or any other suitable system controller having a bus interface. During the initialization, configuration, control, and monitor processes of a conventional FPGA, signals transmitted between the processor and dedicated or shared pads in the FPGA must go through some special intermediate logic that are required in order to interface the FPGA-specific signals to the processor. The FPGA pads cannot be directly connected to the host processor without this special intermediate logic.
SUMMARY OF THE INVENTION
The present invention eliminates the requirement for using special intermediate logic when transmitting signals between an FPGA and a processor. According to the present invention, the FPGA has a dedicated processor interface that provides a uniform interface to the processor during the initialization, configuration, control, and monitor processes. As used in this specification, the term “dedicated” implies that the processor interface is implemented without using any user-defined logic in the FPGA. This interface would also be available after configuring the FPGA and would allow access to user-defined programmable logic inside the FPGA. Thus, the amount of information that can be provided to or received from the FPGA is expanded. The processor interface enables the FPGA to be a memory-mapped peripheral of the processor without having to transmit signals through any external intermediate logic.
REFERENCES:
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5705938 (1998-01-01), Kean
patent: 5737235 (1998-04-01), Kean et al.
patent: 5760604 (1998-06-01), Pierce et al.
patent: 5764080 (1998-06-01), Huang et al.
patent: 5773994 (1998-06-01), Jones
patent: 5825202 (1998-10-01), Tavana et al.
Britton Barry K.
Cunningham Alan
Leung Wai-Bor
Stuby, Jr. Richard G.
Thompson James A.
Lucent Technologies - Inc.
Mendelsohn Steve
Wiley David A
LandOfFree
Field programmable gate array having a dedicated processor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Field programmable gate array having a dedicated processor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field programmable gate array having a dedicated processor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2522549