Field programmable gate array (FPGA) with interconnect encoding

Details Field programmable gate array (FPGA) with interconnect encoding Field programmable gate array (FPGA) with interconnect encoding

1996-06-06

1998-03-03

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 41, 326 39, H03K 19173, H03K 19177

Patent

active

057239843

ABSTRACT:
A method of programing an FPGA to enable encoding of configuration logic block (CLB) outputs enabling an efficient use of FPGA routing resources. The method of the present invention utilizes the one hot approach, wherein only one CLB output is high at a time, to form a state machine using an FPGA. To provide encoding, programmable interconnect points (PIPs) may be programmed to connect CLB outputs to interconnect lines so that the interconnect lines indicate states of the CLB outputs in an encoded form. To provide such encoding, less interconnect lines than CLB outputs provide the encoded form of the CLB outputs. Thus, PIPs can connect a single interconnect line to more than one CLB output. Further, PIPs can connect a single CLB output to interconnect lines provided in separate parallel routing paths. To prevent erroneous results, CLB outputs which are not hot are tri-stated. Output decoding can be provided by an additional decoder in the FPGA connected to the interconnect lines providing the encoded form of the CLB outputs. Output decoding may alternatively be provided using a CLB.

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