Field programmable gate array core cell with efficient logic...

Details Field programmable gate array core cell with efficient logic... Field programmable gate array core cell with efficient logic...

2002-10-11

2004-10-05

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S041000, C326S046000

Reexamination Certificate

active

06801052

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is related to the design of FPGA (Field Programmable Gate Array) core cell designs and, in particular, to core cells based upon LUTs (Look-Up Tables).
FPGAs are integrated circuits whose functions are defined by the users of the FPGA. With shrinking geometries in semiconductor technology, FPGA cores, the main portion of FPGAs after the peripheral circuits have been removed, are also embedded with other defined elements or circuit blocks in ASICs (Application Specific Integrated Circuits). The user programs the FPGA or FPGA core (hence the term, “field programmable”) to perform the functions desired by the user. (Henceforth, the term, FPGA, is used to include both the discrete FPGA device and the FPGA core unless a distinction is specifically made.) The FPGAs have an interconnection network between the logic cells or blocks, and the interconnection network and the logic cells are configurable to perform the application desired by the user. For FPGAs based on SRAM (Static Random Access Memory) cells to hold the configuration bits, the configuration of the FPGA can be repeatedly changed by the user for multiple applications of the electronic system. For FPGAs based on manufacturing mask programming (for example, a via mask), the configuration of the FPGA is performed only once.
In most cases, the logic cells of an FPGA are implemented in the form of a look-up table, rather than an assemblage of programmable logic gates. A look-up table (LUT) with x number of inputs can implement any Boolean logic function of x variables and there are algorithms which can map a given Boolean logic network into a network of LUTs with a minimum delay through the network.
The present invention is directed toward improving the packing of the LUT-based FPGA logic cells so that the FPGA occupies less space for the same degree of functionality. The resulting manufacturing yields of the integrated circuit, either FPGA or ASIC, is increased and costs are lowered. In addition, reducing the number of LUTs required for a given functionality generally increases the speed of the implemented function.
SUMMARY OF THE INVENTION
To achieve these ends, the present invention provides for an integrated circuit having an FPGA core with core cells. Each FPGA core cell comprises a plurality of core cell input terminals and a plurality of core cell output terminals; one or more LUTs, each LUT having an output terminal and a plurality of input terminals, each input terminal of each LUT connected to one of the core cell input terminals; a selectable logic gate having an output terminal and a plurality of input terminals, each input terminal connected to one of said LUT output terminals or to any remaining core cell input terminal not connected to an LUT input terminal; and circuitry selectably connecting the output terminals of the LUTs and the selectable logic gate to the core cell output terminals. The core cell is programmed by setting memory cells or vias in the one or more LUTs, selecting the logic gate and selectably connecting the output terminals of the one or more LUTs and of the selectable logic gate to the core cell output terminals.
To program the core cells for mapping a given Boolean network into the FPGA core, the present invention also provides for the steps of partitioning the logic network into a plurality of cuts, each partitioning cut having no more than the number of core cell input terminals and mapping into logic of the partitioned cut; generating a network graph of each partitioning cut; partitioning input terminals of each partitioning cut into input sets corresponding to input terminals of the LUTs of the core cell in different combinations; generating a network graph for each input partitioning cut for all input combinations; determining equivalence between the network graphs of each partitioning cut, and logic combinations of the partitioning cuts for different logic; and finding an equivalence match for a mapping for logic of each partitioning cut into a logic cell core configured for matching input combination and selected logic gate.


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