Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2002-02-05
2003-09-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S040000, C326S095000, C326S098000
Reexamination Certificate
active
06614258
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to field-programmable gate arrays (FPGAs) and specifically to a FPGA that uses reconfigurable dynamic programmable logic arrays (DPLAs).
BACKGROUND OF THE INVENTION
A PLA (programmable logic array) produces a predetermined set of outputs for a given set of inputs. Each output is a sum-of-products of a subset of the inputs, implemented using an AND plane to generate the product terms and an OR plane to generate the sums of the product terms. A dynamic PLA implements the sum-of-products functions by precharging and conditionally discharging wired-NOR circuits that are built within the AND and OR arrays. These functions are programmed when a dynamic PLA is built such that the array can only produce the same set of output signals for a given set of input signals. A dynamic PLA is “programmable” only in the sense that it is easy to implement desired functions within the array when the array is built but not in the sense that the array can be programmed to provide different functions once the array is built.
Dynamic programmable logic arrays (DPLAs) are utilized extensively. As shown in
FIG. 1
, a DPLA
5
includes input signals
2
to an AND plane
10
whose outputs
18
are then the inputs to an OR plane
14
that produces the output signals
20
. The outputs of the AND plane
10
are known as AND term signals (A
1
to Am). The outputs of the OR plane are known as OR term signals (O
1
to On).
FIG. 1
shows k number of inputs, m number of AND term signals, and n number of OR term signals. The AND plane
10
further comprises multiple NOR term generators
12
, each of which outputs a wired-NOR signal
18
that is first precharged to Vcc (the supply voltage) and then conditionally discharged to GND (the ground voltage). The Vcc and GND can represent high (TRUE) and low (FALSE) logic states, respectively. Similarly, the OR plane
14
also comprises multiple NOR term generators
16
, each of which outputs a wired-NOR signal
20
that is first charged to high logic level and then conditionally discharged to low logic level. For simplicity, the clocks that control the precharge and discharge are not shown in FIG.
1
.
FIG. 2
shows two NOR term generators
12
in the AND plane. The wired-NOR signal
30
is discharged if one or more input signals
2
that are “programmed” to affect this output signal are high. An input signal
2
is programmed to affect an output signal by providing an evaluate circuitry
32
controlled by the input signal
2
.
FIG. 2
shows that the input signals I
1
and I
2
are programmed to affect the AND term signals A
1
and A
2
. If the evaluate circuitry labeled
34
were not provided, for example, then the input signal I
1
cannot affect the AND term signal A
1
while it still affects the AND term signal A
2
.
FIG. 3
shows a conventional evaluate circuitry
38
for DPLA and the precharge transistor
40
and the discharge transistor
42
for the AND term signal. This precharge and conditional discharge circuitry is controlled in two non-overlapping phases, known as precharge and evaluate. During the precharge phase, both CLKP and CLKD are held low so that precharge transistor
40
is turned on and the discharge transistor
42
is turned off, forcing the output signal NL to be high. During the evaluate phase, both CLKP and CLKD are held high so that the precharge transistor
40
is turned off and the discharge transistor
42
is turned on. During the evaluate phase, if the input signal
46
is high to turn on the evaluate transistor
44
, then the charge stored at the output signal NL is discharged via the transistors
44
and
42
, resulting in the signal NL being low. If on the other hand, if the input signal
46
is low during the evaluate phase, the evaluate transistor
44
is turned off and the charge stored at the output signal NL remains high. The input signal
46
must not change during the evaluate phase to avoid falsely discharging the output signal NL.
A NOR term generator
12
, which comprises one precharge transistor and one discharge transistor and at least one evaluate circuitry, works as follows. During the precharge phase, the precharge transistor
40
is turned on and the discharge transistor
42
is turned off, forcing the output signal NL to be high. During the evaluate phase, the precharge transistor
40
is turned off and the discharge transistor
42
is turned on. During the evaluate phase, if one or more input signals that are programmed to affect this output are high, the charge stored at the output signal NL is discharged and NL becomes low. If none of the input signals are high, then there is no path for the charge stored at NL to be discharged and the NL remains high. The NOR term generators
16
in the OR plane
14
works as same as those in the AND plane
10
.
FIGS. 2 and 3
show a DPLA whose output node is precharged to Vcc by a p-transistor and conditionally discharged by two n-transistors in series connected to GND. Alternatively, an n-transistor precharged to GND and conditionally discharged by two p-transistors in series connected to Vcc can be used. Furthermore, the discharge transistor
42
may be omitted if the inputs are guaranteed to be zero or one, if the evaluate transistor is an n-transistor or a p-transistor, respectively, during precharge. Multiple dynamic PLAs can also be connected in a series, known as cascaded dynamic PLAs, such that one signal starts the evaluate phase of the PLAs in succession using self-timed logic.
A detailed description of DPLA can be found in “Principles of C-MOS VLSI Design” by N. H. Weste and K. Eshraghian, Addison-Wesley, 2
nd
Edition, 1993, Chapter 8, pages 595-602 or in the U.S. Pat. No. 4,769,562.
Dynamic PLA with Fine-Grained Control
The evaluate module
38
in
FIG. 3
is replaced with the configurable evaluate module
80
in
FIG. 4
in both the AND and OR planes to provide the complete control of the AND and OR term generators in the resulting PLA. That is, instead of using the evaluate module
38
only in the places where the input signals affect the AND term outputs and in the places where the AND term outputs affect the OR term outputs, a configurable evaluate module
80
is placed in everywhere so that every input signals can affect all AND term outputs and that every AND term output signal can affect all OR term outputs.
The configurable evaluate module
80
comprises an input pass transistor
54
, an evaluate transistor
44
, and an evaluate disable transistor
56
. The control signal C enables either the input pass transistor
54
or the evaluate disable transistor
56
at any given time. When the input pass transistor
54
is turned on, the input signal
46
is allowed to affect the evaluate transistor
44
, such that the evaluate transistor
44
is turned on or off if the input signal
46
is high or low, respectively. When the evaluate disable transistor
56
is turned on instead, the input signal
46
cannot affect the evaluate transistor
44
.
This arrangement of configurable PLA results in a large number of control signals, since each conditional evaluate module
80
requires a dedicated control signal. For a PLA with K number of inputs, M number of AND terms, and N number of OR terms (or the outputs), a total of K×M+M×N=M×(K+N) number of control signals. With such a large number of control signals for a PLA, a preferred method of generating these control signals would be to store the control signals in a memory array (SRAM, DRAM, flash, electrically programmable ROM, electrically erasable programmable ROM, fusible links, or even one-time programmable memory). In this way, the array can be configured to produce any desired function by reading the control signals from the memory array. To avoid falsely discharging the evaluate transistors, the control as well as the input signals must not change during the evaluate phase.
Dynamic PLA with Built-In Configurations
Building the configurations into the array can minimize the required number of control signals. A configurabl
Elan Research
Sawyer Law Group LLP
Tan Vibol
Tokar Michael
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