Electric lamp or space discharge component or device manufacturi – Process – With assembly or disassembly
Reexamination Certificate
2001-11-26
2004-12-28
Patel, Nimeshkumar D. (Department: 2879)
Electric lamp or space discharge component or device manufacturi
Process
With assembly or disassembly
Reexamination Certificate
active
06835111
ABSTRACT:
TECHNICAL FIELD
This invention relates to field emission displays, and, more particularly, to a method and apparatus for reducing power consumption in field emission displays.
BACKGROUND OF THE INVENTION
FIG. 1
is a simplified side cross-sectional view of a portion of a display
10
including a faceplate
20
and a baseplate
21
, in accordance with the prior art.
FIG. 1
is not drawn to scale. The faceplate
20
includes a transparent viewing screen
22
, a transparent conductive layer
24
and a cathodoluminescent layer
26
. The transparent viewing screen
22
supports the layers
24
and
26
, acts as a viewing surface and forms a hermetically sealed package between the viewing screen
22
and the baseplate
21
. The viewing screen
22
may be formed from glass. The transparent conductive layer
24
may be formed from indium tin oxide. The cathodoluminescent layer
26
may be segmented into pixels yielding different colors to provide a color display
10
. Materials useful as cathodoluminescent materials in the cathodoluminescent layer
26
include Y
2
O
3
:Eu (red, phosphor P-56), Y
3
(Al, Ga)
5
O
12
:Tb (green, phosphor P-53) and Y
2
(SiO
5
):Ce (blue, phosphor P-47) available from Osram Sylvania of Towanda PA or from Nichia of Japan.
The baseplate
21
includes emitters
30
formed on a surface of a substrate
32
. The substrate
32
is coated with a dielectric layer
34
that is formed, in accordance with the prior art, by deposition of silicon dioxide via a conventional TEOS process. The dielectric layer
34
is formed to have a thickness that is approximately equal to or just less than a height of the emitters
30
. This thickness may be on the order of 0.4 microns, although greater or lesser thicknesses may be employed. A conductive extraction grid
38
is formed on the dielectric layer
34
. The extraction grid
38
may be, for example, a thin layer of polycrystalline silicon. An opening
40
is created in the extraction grid
38
having a radius that is also approximately the separation of the extraction grid
38
from the tip of the emitter
30
. The radius of the opening
40
may be about 0.4 microns, although larger or smaller openings
40
may also be employed.
In operation, signals coupled to the emitter
30
allow electrons to flow to the emitter
30
. Intense electrical fields between the emitter
30
and the extraction grid
38
then cause field emission of electrons from the emitter
30
. A positive voltage, ranging up to as much as 5,000 volts or more but generally 2,500 volts or less, is applied to the faceplate
20
via the transparent conductive layer
24
. The electrons emitted from the emitter
30
are accelerated to the faceplate
20
by this voltage and strike the cathodoluminescent layer
26
. This causes light emission in selected areas known as pixels, i.e., those areas adjacent to the emitters
30
, and forms luminous images such as text, pictures and the like.
FIG. 2
is a simplified plan view showing rows
42
and columns
44
of the emitters
30
and the openings
40
of
FIG. 1
, according to the prior art. The columns
44
are divided into top columns
44
a
and bottom columns
44
b
, as may be seen in FIG.
2
. Top
46
a
and bottom
46
b
column driving circuitry is coupled to the top
44
a
and bottom
44
b
columns, respectively. A row driving circuit
48
is coupled to odd rows
42
a
and even rows
42
b
. The rows
42
are formed from strips of the extraction grid
38
that are electrically isolated from each other. The columns
44
a
and
44
b
are formed from conductive strips that are electrically isolated from each other and that electrically interconnect groups of the emitters
30
.
By biasing a selected one of the rows
42
to an appropriate voltage and also biasing a selected one of the columns
44
to a voltage that is about forty to eighty volts more negative than the voltage applied to the selected row
42
, the emitter or emitters
30
located at an intersection of the selected row
42
and column
44
are addressed. The addressed emitter or emitters
30
then emit electrons that travel to the faceplate
20
, as described above with respect to FIG.
1
.
Conventional circuitry for driving emitters
30
in field emission displays
10
enables each column
44
once per row address interval and disables each column
44
once per row address interval. The columns
44
present a capacitive load C. Charging and discharging of the capacitance C consumes power in proportion to fCV
2
, where f represents the frequency of charging and discharging the column
44
and V represents the voltage to which the columns
44
are charged. Charging and discharging of the columns
44
in order to drive the emitters
30
forms a major component of the electrical power consumed by the display
10
. As a result, reducing the frequency f, the capacitance C or the voltage V can significantly reduce the electrical power required to operate the display
10
. Displays
10
requiring less electrical power are currently in demand.
There is therefore need for techniques and apparatus that reduce the amount of electrical power required in order to operate field emission displays.
SUMMARY OF THE INVENTION
In one aspect, the present invention includes a field emission display having a substrate and a plurality of emitters formed on the substrate. Each of the emitters is formed on one of a plurality of emitter conductors that is also a row or a column of the display. The display also includes a porous dielectric layer formed on the substrate and the columns. The porous dielectric layer has an opening formed about each of the emitters and has a thickness substantially equal to a height of the emitters above the substrate. The porous dielectric layer is preferably formed by oxidation of porous polycrystalline silicon. The display further includes an extraction grid formed substantially in a plane defined by respective tips of the plurality of emitters. The extraction grid has an opening surrounding each tip of a respective one of the emitters. The display additionally includes a cathodoluminescent-coated faceplate having a planar surface formed parallel to and near the plane of tips of the plurality of emitters.
The porous dielectric results in the emitter conductors having reduced capacitance C compared to prior art dielectric layers. Charging and discharging of the emitter conductors in order to drive the emitters forms a major component of the electrical power consumed by the display. By reducing the capacitance of the emitter conductors, the display is able to form luminous images, such as text and the like, while dissipating reduced electrical power.
In another aspect of the present invention, tips of the emitters are formed from a material having a work function less than four electron volts. The voltage needed in order to drive the emitters, and hence the voltage used to charge and discharge the columns, is proportional to a turn-on voltage for the emitters. Emitters having reduced turn-on voltage draw less electrical power. As a result, baseplates with emitters having low work function tips are able to form luminous images while dissipating reduced electrical power compared to conventional displays.
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patent:
Ahn Kie Y.
Forbes Leonard
Dorsey & Whitney LLP
Patel Nimeshkumar D.
Santiago Mariceli
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