Field effect transistors with vertical gate side walls and...

Details Field effect transistors with vertical gate side walls and... Field effect transistors with vertical gate side walls and...

1998-02-19

2003-07-15

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06593617

ABSTRACT:

TECHNICAL FIELD
The present invention concerns metal-oxide-semiconductor field effect transistors (MOSFETs) in general, and MOSFETs with improved gate oxides and vertical side walls, in particular.
BACKGROUND OF THE INVENTION
The size, shape, and quality of the polysilicon gate of MOSFETs are of particular concern for conventional as well as future scaled-down MOSFETs.
In order to be able to make memory chips and logic devices of higher integration density than currently feasible, one has to find a way to further scale down the gates used in such chips and devices and to improve the accuracy at which such gates are made.
The basic elements of a conventional MOSFET
10
are schematically illustrated in FIG.
1
. Such an FET
10
typically is formed in a silicon substrate
11
and comprises a doped source region
14
and a doped drain region
12
being arranged to the left and right of a polysilicon gate pillar
13
. This gate pillar
13
is separated from the channel
17
—which is situated between the source
14
and drain regions
12
—by an oxide layer
15
. Underneath the polysilicon gate
13
, the oxide layer
15
serves as gate oxide. In conventional FETs, the gate oxide is thicker underneath the polysilicon gate, because the portions of the oxide layer
15
not covered by the polysilicon gate are attacked during the polysilicon RIE, as addressed in the following. Please note that the source/channel and drain/channel junctions
18
are not abruptly defined. The dopant concentration decreases the closer one gets to the actual channel, i.e. the source/channel and drain/channel junctions
18
are not well defined. This is mainly caused by the sloped side walls
16
of the gate
13
which permit dopants to reach the silicon substrate near the gate edges (overlapping the gate) when the source and drain regions
12
and
14
are implanted from the top. The results are increased source and drain resistance, high overlap capacitance, and ill defined effective channel length resulting in degrading the device performance.
In the present state of the art, silicon reactive ion etching (RIE) and a photo-resist mask are used to define the polysilicon gates of MOSFETs, including complementary metal oxide semiconductor (CMOS) FETs. Two requirements have to be satisfied by the RIE process. The polysilicon gates should have perfectly vertical side walls, and furthermore, one has to ensure that the RIE process stops on the gate oxide
15
at the bottom of the polysilicon gate
13
without destroying it. Typically, the gate oxide
15
is very thin (in the range of a few nanometers) and becomes thinner and thinner when further scaling down FETs.
When processing whole wafers, the thickness of the polysilicon layer—which is to be etched to become the polysilicon gate of all MOSFETs on the wafer—varies. To ensure that all polysilicon gates are defined properly, one has to adjust the etch time such that all polysilicon gates, including those formed in a section of the wafer where the polysilicon layer is relatively thick, are etched down to the thin gate oxide
15
. This intentional over-etching, however, leads to a locally reduced thickness of the gate oxide
15
adjacent to the polysilicon gate
13
(as schematically illustrated in FIG.
1
), because the selectivity of the polysilicon etch process is not high enough (please note that high selectivity means that an etch process attacks only the materials it is intended to etch, e.g. the polysilicon in the present example, but not the gate oxide). I.e., conventional polysilicon RIE etch processes not only attack the polysilicon, but also the oxide layer
15
. Due to the low selectivity, the oxide layer
15
is thinner adjacent to the polysilicon gate
13
than the original thickness of the oxide layer (see underneath the polysilicon gate
13
), as schematically illustrated in FIG.
1
.
It is the nature of the currently used RIE polysilicon etch processes that an improved selectivity reduces the directionality of the etch resulting in undesirable non-vertical (sloped) polysilicon gate side walls
16
. In other words, when employing conventional polysilicon RIE processes for the formation of polysilicon gates, either the slope of the side walls increases, or the thin oxide layer
15
is attacked and consequently varies in thickness across the wafer. The polysilicon RIE chemistry can be adjusted to improve the polysilicon/oxide selectivity, but then the RIE etch becomes more isotropic resulting in even more sloped side walls.
As mentioned above, the gate oxide has to become thinner when scaling down the MOSFETs. It is immediately obvious that the thinner the gate oxide is, the less over-etching is acceptable. In other words, the etch selectivity has to be improved in order to be able to make polysilicon gates of very small size. The gate oxide of sub-0.1 micron CMOS FETs, for example, is less than 3 nm thick. Any over-etching impairs the device performance.
The present patent application is related to U.S. patent application Ser. No. 09/026,094 entitled “FIELD EFFECT TRANSISTORS WITH IMPROVED IMPLANTS AND METHOD FOR MAKING SUCH TRANSISTORS”, and U.S. patent application Ser. No. 09/026,094 entitled “METHOD FOR MAKING FIELD EFFECT TRANSISTORS HAVING SUB-LITHOGRAPHIC GATES WITH VERTICAL SIDE WALLS”, both filed on the same day and presently assigned to the assignee of the instant application. The disclosure of these two patent applications is incorporated herein by reference.
There are currently no MOSFET fabrication schemes known that would allow to realize MOSFETs with vertical (non-sloped) side walls. Furthermore, the conventional techniques are not suited to make scaled-down FETs having intact gate oxides with a thickness of less than 5 nm.
It is an object of the present invention to provide MOSFETs having a well defined channel length, minimum source and drain resistance, and minimum overlap capacitance.
It is a further object of the present invention to provide MOSFETs of scaled-down size, and in particular MOSFETs of size smaller than 0.1 &mgr;m.
It is another object of the present invention to provide a method for the formation of MOSFETs with well defined channel length, minimum source and drain resistance, and minimum overlap capacitance.
It is another object of the present invention to provide a method for the formation of MOSFETs of scaled-down size, and in particular MOSFETs of size smaller than 0.1 &mgr;m.
SUMMARY OF THE INVENTION
The above objectives have been accomplished by the provision of a new and inventive method for the formation of FETs. This method comprises the following steps of:
forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer;
defining an etch window having the lateral size and shape of a gate pillar to be formed;
defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process;
depositing a gate conductor such that it fills the gate hole;
removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole;
removing at least part of the dielectric stack.
The inventive approach substitutes part of the conventional MOS or CMOS process steps usually employed for the definition of the gate conductor by the above sequence of steps.
The above process can be modified in different ways as will be addressed in the detailed description.
Advantages will become obvious form the detailed description and the drawings. Some advantages, however, are that the side walls of the gate pillars are vertical. It is another advantage of the inventive structure that the thickness of the SiO
2
pad oxide is homogeneous, i.e., the thickness of the pad oxide is uniform on top of the source and drain regions and does not vary across the wafer. This in turn ensures that there is no variation in source and drain junction depth across the wafer. In conventional devices where the pad oxide thickness varies, the source and drain junction depth is not uniform. This is of particular importance f

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