Field effect transistors (FETs) with multiple and/or...

Details Field effect transistors (FETs) with multiple and/or... Field effect transistors (FETs) with multiple and/or...

2007-12-18

2007-12-18

Smith, Zandra V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000, C257S382000, C438S305000, C438S306000, C438S303000, C438S301000, C438S231000

Reexamination Certificate

active

10908087

ABSTRACT:
A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

REFERENCES:
patent: 5962895 (1999-10-01), Beyer et al.
patent: 2002/0008295 (2002-01-01), Yang et al.
patent: 2002/0137268 (2002-09-01), Pellerin et al.

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