Field effect transistor with reduced gate delay and method...

Details Field effect transistor with reduced gate delay and method... Field effect transistor with reduced gate delay and method...

2001-05-02

2004-09-28

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S407000, C257S413000

Reexamination Certificate

active

06798028

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to field effect transistors and integrated circuits and, particularly, to a field effect transistor (FET) having a gate electrode with a reduced gate resistance and a method for fabricating the same.
2. Description of the Related Art
The manufacturing process of integrated circuits (ICs) involves the fabrication of numerous semiconductor devices, such as insulated gate field effect transistors, on a single substrate. In order to provide increased integration density and an improved device performance of the field effect transistors, for instance, with respect to signal processing time and power consumption, feature sizes of the field effect transistors are steadily decreasing. In general, decreasing feature sizes, such as the gate length of the field effect transistor, provide a variety of advantages, for example, high package density and small rise and fall times during switching of the transistors due to the reduced gate length and, hence, the reduced channel length. Reducing the gate length of the FET beyond a certain size, however, may result in disadvantages that act to offset advantages obtained by the reduced channel length, e.g., the resistance of the gate electrode having the reduced gate length increases with decreasing gate length. As a result, a delay of the voltage applied to the gate electrode for controlling the channel can be observed. Especially in modern ultrahigh density circuits, the gate length is trimmed down to 100 nm or less, so that the available gate cross-section for transmitting the voltage applied to the gate electrode is not sufficient to insure the high-speed signal transmission required for obtaining the fast switching times of modern integrated circuits, such as microprocessors driven by clock frequencies of 1 GHz and more.
To clearly demonstrate the problems involved with steadily decreasing feature sizes of modern ultra-high density integrated circuits, a typical prior art process flow will be described with reference to
FIGS. 1
a
-
1
d
, in which the problems involved with the formation of the gate electrode are detailed. As the skilled person will easily appreciate, the figures depicting the typical prior art process flow and the typical prior art device are merely of a schematic nature, and transitions and boundaries illustrated as sharp lines may not be imparted as sharp transitions in a real device. Furthermore, the description of the typical prior art process and device refers to standard manufacturing procedures without specifying typical process parameter values used for these procedures, since individual processing steps may be accordingly adapted to meet specific design requirements. Moreover, only the relevant steps and features of the transistor device are shown in the figures.
In
FIG. 1
a
, a schematic cross-sectional view of a field effect transistor manufactured in accordance with a typical CMOS processing is illustrated. In
FIG. 1
a
, a field effect transistor
100
is schematically shown in a manufacturing stage prior to patterning a gate electrode. In a silicon substrate
101
, shallow trench-isolations
102
define an active region
106
. A gate insulation layer
103
separates a polysilicon layer
104
from the active region
106
. On the polysilicon layer
104
, a photoresist layer
105
is patterned.
The formation of the structure shown in
FIG. 1
a
may be accomplished using the following process steps. After defining the active region
106
by forming the shallow trench isolations
102
, the gate insulation layer
103
is thermally grown on the substrate. Thereafter, a polycrystalline silicon (polysilicon) layer
104
is deposited over the gate insulation layer
103
. Then, a photoresist layer is deposited on the polysilicon layer
104
, and it is patterned by photolithography using deep ultraviolet exposure light to result in the patterned photoresist layer
105
.
FIG. 1
b
schematically shows a cross-sectional view of the field effect transistor
100
of
FIG. 1
a
in an advanced manufacturing stage. In
FIG. 1
b
, a gate electrode
107
is formed over the active region
106
, and it is separated therefrom by the gate insulation layer
103
. The gate electrode
107
has been formed from the polysilicon layer
104
by anisotropic etching using the photoresist layer
105
as a mask. A lateral extension of the gate electrode
107
in a transistor length dimension, indicated by the arrows
108
and
109
and also referred to as the gate length, is determined by the lithography step and by a subsequent etch trim process performed to further reduce the gate length. A gate height, indicated by arrow
110
, is determined by the thickness of the polysilicon layer
104
. According to this typical prior art processing, the gate length on the top
120
of the gate electrode
107
, as indicated by arrow
109
, is essentially equal to the gate length at the foot or bottom
141
of the gate electrode
107
, represented by arrow
108
.
As can be seen from
FIG. 1
b
, the cross-section of the gate electrode
107
is of substantially rectangular shape and the effective cross-section available for charge carrier transportation decreases, as the gate length is scaled down. Moreover, the gate voltage for controlling the channel to be formed in the active region
106
is applied by contact portions that are outside of the active region in the transistor width dimension, which is the dimension extending along a line normal to the drawing plane of
FIG. 1
b
. Accordingly, the effective sheet resistance of the gate electrode depends on the gate length on the top portion
120
of the gate electrode
107
, and, more particularly, the gate sheet resistance increases as the gate length decreases.
FIG. 1
c
schematically shows a cross-section of the final field effect transistor
100
. In the active region
106
, drain and source regions
111
are formed and separated in the transistor length dimension by a channel
114
. Sidewall spacers
112
are formed on the sidewalls of the gate electrode
107
and extend along the transistor width dimension. At the top surfaces of the drain region, the source region and the gate electrode, portions
113
of materials having a reduced electrical resistance, for example, consisting of cobalt silicide, are formed.
The portion
113
of reduced electrical resistance above the gate electrode
107
is also of substantially rectangular shape and, therefore, exhibits a gate area available for charge carrier transportation, i.e., cross-section that is small, particularly when the gate length is trimmed down to dimensions of 100 nm and beyond. Since the thickness of the polysilicon layer
104
and, hence, the height of the gate electrode
107
, is limited to about 1500-2000 Å with respect to stability of the gate electrode, polysilicon delamination and the like, the transistor
100
suffers from higher gate resistance when the gate length is reduced, thereby significantly deteriorating the performance of the transistor.
In view of the above problems, a need exists for a field effect transistor device having a reduced gate resistance, and for a method for fabricating the gate electrode with reduced gate resistance.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a transistor comprises a substrate, an active region defined in the substrate, a gate insulation layer formed above the active region, and a gate electrode formed above the gate insulation layer. The gate electrode comprises a middle portion located over the active region, wherein the middle portion has a gate length and a gate height. A cross-sectional area in a plane defined by the gate length and the gate height of the middle portion exceeds a value obtained by multiplying the gate length by the gate height.
As is common practice, the gate length is herein defined as the lateral extension at the bottom of the middle portion of the gate electrode. The middle portion indicates that part of the gate electrode is located over the channel regio

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