Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-10-20
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S243000, C438S411000, C438S421000, C438S422000
Reexamination Certificate
active
06376286
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to silicon on insulator (SOI) field effect transistor structures, and more specifically to such structures formed on a conventional silicon bulk wafer.
BACKGROUND OF THE INVENTION
Conventional or bulk semiconductor devices are formed in semiconductive material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semi-conductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate and “off” state leakage from the drain to the source both increase power consumption. Junction capacitance also slows the speed at which a device using such transistors can operate. These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance problem, silicon on insulator technology (SOI) has been gaining popularity. However, SOI field effect transistors suffer from floating body effects. The floating body effect occurs because the channel, or body, of the transistor is not connected to a fixed potential and, therefore the body takes on charge based on recent operation of the transistor. The floating body effect causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate. This problem is particular apparent for passgate devices such as those used in dynamic random access memory (DRAM) wherein it is critical that the threshold voltage remain fixed such that the transistor remains in the “off” position to prevent charge leakage from the storage capacitor.
Accordingly, there is a strong need in the art for a semiconductor field effect transistor structure, and a method for forming such structure, that includes the low junction capacitance and low “off” state leakage characteristics of the SOI FET but does not suffer the disadvantages of a floating body potential.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a method of forming a field effect transistor on a semiconductor substrate which includes etching an insulating trench around the perimeter of an active region of said transistor to isolate the active region from other structures on said substrate and etching an insulating undercut in the bottom of the insulating trench to isolate at least a portion of the bottom surface of the active region from the substrate. Portions of the active region may be doped to form each of a source region and a drain region on opposing sides of a central channel region. The insulating undercut may isolate at least a portion of both the source region and the drain region from the silicon substrate. Furthermore, the insulating undercut may isolate at least a portion of the central channel region from the silicon substrate.
Etching the undercut includes: a) forming a protective layer on the side walls and bottom of the trench; b) performing a vertical anisotropic etch of said layer to remove such layer to expose silicon substrate at the bottom of the trench; and c) performing an isotropic etch of the silicon substrate to form said undercut. The isotropic etch may be performed using a KOH wet etch. The protective layer may be silicon dioxide and filling the undercut may include performing a chemical vapor deposition using at least one of SiH4 and TEOS.
A second object of this invention is to provide a field effect transistor formed on a semiconductor substrate which includes an active region, including a central channel region and a source region and a drain region disposed on opposite sides of said central channel region, a bridge region, with a cross section area smaller than a cross section of the active region, consecutively coupling the central channel region with said semiconductor substrate; and an insulator isolating said active region and said bridge region from other structures formed on said semiconductor substrate. The central channel region, the bridge region, and the semiconductor substrate may all be the same conductivity and the source region and drain region may be of an opposite conductivity. The insulator may extend under a bottom surface of the active region to at least partially isolate the source region and the drain region from the silicon substrate such that the semiconductor junctions between the source region and the silicon substrate and the drain region and the silicon substrate are at least one of reduced in size or eliminated. The insulator may be silicon dioxide.
A third object of this invention is to provide a semiconductor device including a plurality of field effect transistors formed on a semiconductor substrate, each transistor including: a) an active region, including a central channel region and a source region and a drain region each on opposing sides of the central channel region; b) a bridge region, with a cross section area smaller than a cross section of the active body region, conductively coupling the central channel region with said semiconductor substrate; and c) an insulator isolating said active body region and said bridge region from at least one other of said plurality of transistors. The central channel region, the bridge region, and the semiconductor substrate all may be the same conductivity and the source region and drain region may be of an opposite conductivity. The insulator may extend under a bottom surface of the active region to at least partially isolate the source region and the drain region from the silicon substrate such that the semiconductor junctions between the source region and the silicon substrate and the drain region and the silicon substrate are at least one of reduced in size or eliminated. The insulator isolating at least two of the plurality of transistors may be silicon dioxide.
REFERENCES:
patent: 4571609 (1986-02-01), Hatano
patent: 4682407 (1987-07-01), Wilson et al.
patent: 4683637 (1987-08-01), Varker et al.
patent: 4888300 (1989-12-01), Burton
patent: 5097312 (1992-03-01), Bayraktaroglu
patent: 5262346 (1993-11-01), Bindal et al.
patent: 5324671 (1994-06-01), Bayraktaroglu
patent: 5391503 (1995-02-01), Miwa et al.
patent: 5401998 (1995-03-01), Chiu et al.
patent: 5466630 (1995-11-01), Lur
patent: 5489792 (1996-02-01), Hu et al.
patent: 5494837 (1996-02-01), Subramanian et al.
patent: 5543338 (1996-08-01), Shimoji
patent: 5618345 (1997-04-01), Saitoh et al.
patent: 5620912 (1997-04-01), Hwang et al.
patent: 5674760 (1997-10-01), Hong
patent: 5683932 (1997-11-01), Bashir et al.
patent: 5702989 (1997-12-01), Wang et al.
patent: 5801397 (1998-09-01), Cunningham
patent: 5804856 (1998-09-01), Ju
patent: 5811855 (1998-09-01), Tyson et al.
patent: 5825696 (1998-10-01), Hidaka et al.
patent: 5846857 (1998-12-01), Ju
patent: 5877046 (1999-03-01), Yu et al.
patent: 5879975 (1999-03-01), Karlsson et al.
patent: 5894152 (1999-04-01), Jaso et al.
patent: 5907768 (1999-05-01), Malta et al.
patent: 5963789 (1999-10-01), Tsuchiaki
patent: 5972758 (1999-10-01), Liang
patent: 5976945 (1999-11-01), Chi et al.
patent: 5977579 (1999-11-01), Noble
patent: 6004864 (1999-12-01), Huang et al.
patent: 6008104 (1999-12-01), Schrems
patent: 6066527 (2000-05-01), Kudelka et al.
patent: 0 480 373 (1991-10-01), None
S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era, vol. 1, p. 531.
Advanced Micro Devices , Inc.
Bowers Charles
Renner , Otto, Boisselle & Sklar, LLP
Schillinger Laura
LandOfFree
Field effect transistor with non-floating body and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Field effect transistor with non-floating body and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field effect transistor with non-floating body and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2870124