Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-29
2001-03-20
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S206000, C257S207000, C257S208000, C257S390000, C257S412000, C257S387000
Reexamination Certificate
active
06204542
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device for use in a semiconductor integrated circuit, and more particularly, to a field effect transistor whose current driving capability is improved without causing a reduction in the integration density, and also to a method of increasing the current driving capability of a field effect transistor. The invention also relate to a basic cell including a field effect transistor with improved current driving capability. Furthermore, the invention relates to a method of designing a mask layout for such a transistor or basic cell.
2. Description of the Related Art
FIG. 1
is a plan view illustrating a layout of a conventional MOSFET (metal oxide semiconductor field effect transistor). In
FIG. 1
, reference numeral
14
denotes an active region formed in the surface of a semiconductor substrate. A gate electrode
13
is formed over the active region via a gate insulating film. A channel region of the transistor is formed in the portion of the active region under the gate electrode. In other words, the portion of the gate electrode
13
overlapping, or located over, the active region
14
serves to define the channel region. Diffusion regions containing an impurity providing a desired type of conduction are formed in the active region on both sides of the channel region. One of these diffusion regions is called a drain region
11
and the other a source region
12
. An isolation region
16
is formed around the active region. In
FIG. 1
, contact holes are formed at square-shaped regions
15
. In the embodiment shown in
FIG. 1
, there are three contact holes: a contact hole D used for contacting to the drain region; a contact hole S used for contacting to the source region; and a contact hole G used for contacting to the gate electrode.
In the transistor according to the embodiment described above, if a proper voltage is applied between the gate electrode and the substrate, a channel is formed in the channel region. In other words, the portion of the gate electrode located over the active region serves as an intrinsic gate, that is, serves to form the channel. If a proper voltage is further applied between the drain and the source, then current flows between the drain and the source. The current driving capability of the transistor is defined by the current that flows when voltages specified depending on the conditions required in a particular application are applied to the gate, source, and drain, respectively. A transistor having higher current driving capability can operate at a higher speed.
A typical process for producing such a field effect transistor is described below. First, isolation regions are formed in the principal surface of a semiconductor substrate by various methods, including the LOCOS (local oxidation of silicon) method, the trench isolation method, or the like. Regions surrounded by the isolation regions will become the active regions in which transistors or other elements are formed. In the case where a CMOS (complementary metal-oxide-silicon) integrated circuit is produced, p-wells and/or n-wells are also formed in the principal surface of the semiconductor substrate. Subsequently, a gate insulating film is formed on the surface of the active region. Furthermore, for example, a polycrystalline silicon film is deposited on the gate insulating film. The polycrystalline silicon film is patterned into the form of a gate electrode. Diffusion regions are then formed in the active region, at both sides of the gate electrode, thereby forming a source region and a drain region. More specifically, the diffusion regions of the source and drain regions are formed, for example, by implanting an impurity of a proper conduction type into the active region using the gate electrode as an implantation mask so that only the area of the active region which is not covered by the gate electrode is implanted with the impurity. Thus, a MOSFET is obtained.
Furthermore, additional source and drain regions may also be formed as follows. After performing ion implantation using the gate electrode as the mask, a gate side wall film with a particular thickness is formed on each side wall of the gate electrode. Ion implantation is again performed at a different energy and to a different concentration, thereby forming source and drain regions below the gate side wall films and on the outside thereof with different depths and impurity concentrations. For example, the impurity concentration in the areas below the gate side wall films is set lower than that of the outer regions so as to reduce the electric field at the drain edge thereby suppressing generation of hot carriers. This type of MOSFET is called an LDD (lightly doped drain) MOSFET. In the example shown in
FIG. 1
, gate side wall films
18
are formed on the sides of the gate electrode
13
.
Furthermore, the transistor formed according to the process described above is covered with an insulating film. Holes are then formed in the insulating film at proper locations so as to form contact holes for connections to the gate, source, and drain, respectively. After forming a plug in each contact hole, interconnections are formed on the insulating film whereby the transistor is connected to other transistors or elements.
The length of the channel region, that is, the spacing between the source and drain is generally called a channel length. The channel length is determined by the gate length, that is the lateral size, i.e., L in
FIG. 1
, of the part of the gate electrode over the active region. For this reason, the gate electrode is formed so that it has a fixed width over the active region. On the other hand, the contact to the gate electrode is made in a portion of the gate electrode that extends over the isolation region and has a greater width. The width of the channel region, that is, the length measured along the boundary between the channel region and the source or the drain is called a channel width. The channel width is determined by the gate width, that is, the longitudinal size, i.e., W in
FIG. 1
, of the part of the gate electrode located over the active region. The current driving capability of the transistor increases with the reduction in the gate length and with the increase in the gate width. However, the minimum gate length is limited by the process technology. Thus, to produce a transistor with a high current driving capability, it is required to increase the gate width, that is, the length, i.e., longitudinal size, of the part of the gate electrode located over the active region.
In semiconductor integrated circuits, a large number of such transistors are formed on the surface of a semiconductor substrate, and they are connected to one another via contacts. In most cases, a plurality of transistors, for example two transistors, are formed in one active region, although one transistor is formed in the active regions shown in FIG.
1
. It is also well known in the art to dispose basic cells, each of which includes a particular number of transistors, into an array form so as to form a cell array and then properly connect the transistors in the cell array thereby forming a desired circuit. In this technique, it is also known to form contacts at grid points disposed at fixed intervals so as to achieve more efficient connections.
FIG. 2
illustrates an example of a basic cell, as disclosed in
FIG. 10
of U.S. Pat. No. 5,436,485, which includes two n-channel transistors and two p-channel transistors. In this basic cell, contact holes may be formed at any contact areas at uniformly spaced grid points in an X-Y plane. In
FIG. 2
, contact areas are denoted by squares. Specifically, three contact areas are arranged on each line in the X direction and ten contact areas are arranged in each line in the Y direction. Thus, a total of thirty contact areas
97
,
106
-
111
,
115
,
124
-
129
, are provided wherein a contact may be formed in any desired contact area. In this basic cell, active regions
194
and
212
are each formed into
Iida Shigeo
Kimura Yoshitaka
Kinoshita Eita
Abraham Fetsum
Kawasaki Steel Corporation
Oliff & Berridg,e PLC
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