Field effect transistor with double sided airbridge

Details Field effect transistor with double sided airbridge Field effect transistor with double sided airbridge

1999-09-08

2001-03-13

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S419000, C257S433000

Reexamination Certificate

active

06201283

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to field effect transistors, and more particularly to a field effect transistor with a double sided airbridge.
2. Description of the Prior Art
A conventional field effect transistor (hereinafter referred to as an FET) includes a semiconductor substrate (reference numeral
1
in
FIGS. 1
a
and
1
b
) with conductive layers or insulating layers disposed on the substrate. A gate electrode is provided to modulate the current flowing through a channel from a drain electrode to a source electrode in response to a radio frequency (RF) electrical signal applied thereto. Most commonly, the gate is fed from the end with the RF modulating signal which travels the length of the gate stripe.
One use of such an FET is as a low noise amplifier. An example of an FET is shown in FIG.
1
and found in IEEE Transactions On Electron Devices, Vol. ED-31, No. 12, Dec. 1985, pgs. 2754-2759, “Airbridge Gate FET For GaAs Monolithic Circuits”. In such article a single airbridge structure
6
is formed over the source electrode
4
. The airbridge
6
is T-shaped in plan view and connects the relatively small gate pad
2
b
at the base of the T at one side of the source strip contact
4
and the narrow gate finger electrode
2
a
along its whole width at the top of the T. Electric power is supplied to the small stepped gate pad
2
b
in the FET with the current flowing through outwardly fanned paths to the much wider gate finger electrode
2
a
. However, the airbridge
6
and the source electrode
4
cross each other over a large area as shown in
FIG. 1
a
. Thus, even though an airbridge structure is used, an increase in gate capacitance is created which decreases performance at high frequencies. More importantly, during fabrication of the single airbridge, a large stress is exerted on the extremely narrow gate finger
2
a
. This stress can be considered visually as a force vector angled upwards and to the right on the junction of the gate finger
2
a
and the substrate
1
as shown in
FIG. 1
b
. Thus, this large force applied to the small gate finger junction area results in extreme stress exerted on the relatively small base portion of gate finger. This reaction reduces the relatively weak gate finger structural bond with the substrate so that the metal gate structure tends to lift off during fabrication of the FET. Also, the electrical resistance of the single airbridge gate is significant which decreases the cut-off frequency of the FET.
Another example of a field effect transistor is illustrated in
FIG. 2
, and found in U.S. Pat. No. 5,019,877, “Field Effect Transistor”, by Kenji Hosogi. In such patent the field effect transistor with its substrate
1
, drain electrode
3
and source electrode
4
includes a narrow airbridge wiring structure
6
that resembles a raised narrow elongated conductor which connects adjacent feeding points
5
on a gate finger
2
a
longitudinally along the width of the airbridge. Although the narrow airbridge with its narrow footprint reduces resistance and capacitance of the structure, such an FET, however, has a propagation time delay and a relatively high gate resistance.
What is needed, therefore, is an FET in which includes an airbridge portion of a gate electrode that reduces the structural stress on the relatively small central gate finger portion and which provides a lower gate resistance.
SUMMARY OF THE INVENTION
The preceding and other shortcomings of the prior art are addressed and overcome by the present invention which provides a field effect transistor comprising a substrate containing a conductive region, conductive source and drain electrodes disposed on the substrate on the conductive region, and a conductive gate electrode disposed on the substrate. The gate electrode includes a central narrow finger portion with a first end at the conductive region between the source and the drain electrodes and a second end. A double sided airbridge portion flares outwardly from the second end and resembles wings or the letter T in front view and is generally rectangular in plan view. A first gate pad is disposed on the substrate outwardly from the source electrode and is connected physically and electrically to, and along the width of, one extremity of the airbridge and a second gate pad is disposed on the substrate outwardly from the drain electrode and is physically and electrically connected to, and along the width of, the second extremity of the airbridge. Hence, FET the gate pads support the opposed outermost extremities of the winged airbridge which reduces the stress on the centrally positioned and relatively narrow gate finger, especially during fabrication. The airbridge serves to reduce the electrical gate resistance characteristic of the field effect of the FET with each end of the winged portions effectively providing parallel resistance paths. In operation the first and second gate pads receive and transmit signals to and from the gate finger portion to modulate current flowing from the source to the drain electrodes. The FET is generally used at microwave or millimeter wave frequencies.
The foregoing and additional features and advantages of this invention will become apparent from the detailed description and accompanying drawing figures below. In the figures and the written description, numerals indicate the various elements of the invention, like numerals referring to like elements through both the drawing figures and the written description.


REFERENCES:
patent: 3475234 (1969-10-01), Kerwin
patent: 5019877 (1991-05-01), Hosogi
patent: 5247201 (1993-09-01), Becker
Ezio M. Bastida, “Airbridge Gate FET1for GaAs Monolithic Circuits”, IEEE Transactions on Electron Devices, vol. Ed. 72, No. 12, Dec. 1985.

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