Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Patent
1998-10-01
2000-05-16
Bowers, Charles
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
438424, 438425, 438296, H01L 2176
Patent
active
060636947
ABSTRACT:
Into the portion of a silicon substrate which lies in the vicinity of a trench isolation portion, ions such as argon for enhancing the oxidation rate are implanted. Or, nitrogen ions for lowering the oxidation rate are implanted into the portion of the silicon substrate other than the portion thereof lying in the vicinity of the trench isolation portion. Thereafter, thermal oxidation is performed, so that a gate insulation film is formed in such a manner that the thickness thereof becomes equal to or greater than the thickness of the center portion thereof. Thus, the deterioration of the breakdown voltage of the insulation film can be prevented, because the gate insulation film becomes thin in the end portion of the gate electrode.
REFERENCES:
patent: 4374011 (1983-02-01), Vora et al.
patent: 4580331 (1986-04-01), Socolf
patent: 5130268 (1992-07-01), Liou et al.
patent: 5258332 (1993-11-01), Horika et al.
patent: 5372951 (1994-12-01), Anjum et al.
patent: 5525540 (1996-06-01), Zenke et al.
patent: 5561073 (1996-10-01), Jerome et al.
patent: 5578509 (1996-11-01), Fujita
patent: 5643822 (1997-07-01), Furukawa et al.
patent: 5677229 (1997-10-01), Morita et al.
patent: 5728614 (1998-03-01), Tseng
patent: 5733383 (1998-03-01), Fazan et al.
patent: 5741738 (1998-04-01), Mandelman et al.
patent: 5780346 (1998-07-01), Arghavani et al.
patent: 5795811 (1998-08-01), Kim et al.
patent: 5811347 (1998-09-01), Gardner et al.
patent: 5874346 (1999-02-01), Fulford, Jr. et al.
patent: 5891787 (1999-04-01), Gardner et al.
patent: 5940718 (1999-08-01), Ibok et al.
C.T. Liu, et al., "25.ANG. Gate Oxide Without Boron Penetration For 0.25 and 0.3-.mu.m PMOSFETs", IEEE, 1996 Symposium on VLSI Technology Digest of Technical Paper, Jul. 1996, pp. 18 and 19.
Extended Abstracts (The 58th Autumn Meeting, 1997); The Japan Society of Applied Physics, 1997, No. 2, JSAP Catalog No.: AP971120-02.
Blum David S
Bowers Charles
NEC Corporation
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