Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-15
2002-06-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000
Reexamination Certificate
active
06407428
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the design of field effect transistors (FETs) using silicon-on-insulator (SOI) technology and, more particularly, to an SOI FET with a structure for controlling short channel effects.
BACKGROUND OF THE INVENTION
Conventional or bulk semiconductor devices are formed in semiconductive material by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). When a given chip uses both P-type and N-type, it is known as a complimentary metal oxide semiconductor (CMOS). Each of these transistors must be electrically isolated from the others in order to avoid shorting the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various transistors. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate increase power consumption, require higher threshold voltages, and slows the speed at which a device using such transistors can operate (e.g. degrades frequency response). These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
In order to deal with the junction capacitance problem and improve frequency response, silicon on insulator technology (SOI) has been gaining popularity. A SOI wafer is formed from a bulk silicon wafer by using conventional oxygen implantation techniques or wafer bonding techniques to create an insulating buried oxide layer at a predetermined depth below the surface. Between the buried oxide layer and the surface of the SOI wafer is a silicon device layer in which SOI field effect transistors (FETs) and other SOI structures may be fabricated.
Referring to
FIG. 1
, a partially depleted SOI FET
10
is shown. The FET
10
is fabricated on an SOI wafer
12
which includes a bulk substrate
14
, an insulating buried oxide layer
16
, and the device layer
18
. The FET
10
is fabricated within the device layer
18
and includes a source region
20
and a drain region
22
each of a first conductivity silicon and a channel region
24
, of the opposite conductivity silicon, positioned between the source region
20
and the drain region
22
. A gate
26
is positioned above the channel region
24
and is separated from the channel region
24
by an insulating gate oxide film
28
. In operation, when a charge above a threshold voltage is applied to the gate
25
, current flows from a source extension region
20
′ to a drain extension region
22
′ through a narrow depletion region
24
′ just beneath the gate oxide
28
.
It is desirable to reduce the size of the FET
10
such that a greater quantity of such FETs may be fabricated within a particular size wafer. A problem associated with reducing the size of SOI FET structures is a reduction in the length of the depletion region
24
′ (distance between the source extension
20
′ and the drain extension
22
′) degrades FET performance because of a phenomenon known as the short channel effect. When the length of the depletion region
24
′ is on the order of 0.2 &mgr;m, the potential of both the source region
20
and the drain region
22
will cause depletion within the depletion region
24
independent of the potential of the gate
26
. The depletion regions formed by potential of the source region
20
and the drain region
22
may extend entirely through the depletion region
24
′ permitting current to flow even though the potential of the gate
26
is below threshold potential in a phenomenon referred to as punch-through. Additionally, impact ionization within the channel region
24
caused by the floating body effect further degrades short channel performance of the FET
10
.
It has been found that short channel behavior is governed by the ratio of the depletion region
24
thickness (depth below the gate oxide
28
) to its length. As such, decreasing the thickness of the gate oxide region
28
enables use of a thinner depletion region
24
for improving short channel performance. However, tunneling leakage is a problem with thin gate oxide regions
28
, particularly when the channel region
24
is P- conductivity silicon.
The thickness of the depletion region
24
, can also be decreased by increasing the doping concentration of the channel region
24
. It has been found that the thickness of the depletion region is inversely proportional to the square root of the channel doping concentration. However, increased doping concentrations tend to increase junction capacitance which degrades the FET's frequency response.
Accordingly, there is a strong need in the art for a semiconductor field effect transistor structure which can be scaled to sub-micron dimension without significant performance degradation due to short channel effect or increased junction capacitance.
SUMMARY OF THE INVENTION
A first aspect of the present invention is to provide a silicon-on-insulator (SOI) field effect transistor (FET) on an SOI wafer which includes a silicon device layer separated from a bulk silicon layer by an insulating layer of silicon dioxide. The SOI FET comprises a channel region of a first conductivity type semiconductor formed in the silicon device layer. A source region and a drain region, both of a second conductivity type semiconductor, are formed in the silicon device layer on opposing sides of the channel region. A buried and confined metal plate region is positioned within the central portion of the central channel region. The buried and confined metal plate region extends between the source region and the drain region and is separated from a top surface of the central channel region leaving a depletion region there between and is separated from a bottom surface of the channel region. A gate is positioned above the central channel region, separated from the top surface of the central channel region by a gate oxide layer, for controlling depletion within the depletion region.
The source region and the drain region may include a source extension region and drain extension region respectively. Both extension regions extending into the central channel region adjacent to the top surface of the central channel region. The buried and confined metal plate region extends between the source extension region and the drain extension region at a depth that corresponds to the depth of the source extension region and drain extension region (e.g. junction depth). More specifically, the plate region has a top surface and a bottom surface (defined by a cut-off concentration) both of which are substantially parallel with the top surface of the central channel region, and the bottom surface of the plate region is positioned at a depth corresponding to the junction depth.
In the exemplary embodiment a thickness of the plate region, between the top surface of the plate region and the bottom surface of the plate region, is between 50 and 150 angstroms, or more specifically, between 80 and 120 angstroms in thickness.
A second aspect of the present invention is to provide a method of fabricating an SOI FET. The method comprises: a) forming a body region within a device layer of a silicon on insulator wafer; b) forming a gate over a central channel region of the body region; c) forming a source region and a drain region on opposing sides of the central channel region; and d) forming a heavily doped buried and confined metal plate region within the central channel region and extending between the source region and the drain region.
The step of forming the body region may include forming an insulating trench about a periphery of the body region to isolate the body from other portions of the silicon device layer.
The step of forming the source region and the drain region may include: i) lightly doping t
An Judy Xilin
Krishnan Srinath
Advanced Micro Devices , Inc.
Le Bau
Nelms David
Renner Otto Boisselle & Sklar
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