Field effect transistor process with semiconductor mask, single

Details Field effect transistor process with semiconductor mask, single Field effect transistor process with semiconductor mask, single

1996-07-22

1999-08-17

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

438571, 438949, 438951, H01L 21338

Patent

active

059406941

ABSTRACT:
A method for fabricating a periodic table group III-IV field-effect transistor device is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent semiconductor material secondary mask element, a mask element which can be grown epitaxially during wafer fabrication. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

REFERENCES:
patent: 3764865 (1973-10-01), Napoli et al.
patent: 3855690 (1974-12-01), Kim et al.
patent: 3861024 (1975-01-01), Napoli et al.
patent: 3943622 (1976-03-01), Kim et al.
patent: 4961194 (1990-10-01), Kuroda et al.
patent: 5770489 (1998-06-01), Onda
Etch Rates and Selectivities of Citric Acid/Hydrogen Peroxide on GaAs, Alo.3Ga 0.7As, In 0.2Ga 0.8As, In 0.53Ga 0.47As, In 0.52Al0.48As, and In P, authored by G.C. DeSalvo et al., p. 831 in the J. Electrochem. Soc., vol. 9, No. 3, Mar. 1992.
Citric Acid Etching of Ga AS1-33 Sb.times., Al0.5Ga 0.5Sb, and InAs for Heterostructure Device Fabrication, authored by G.C. DeSalvo et al., p. 3526 in the J. Electrochem. Soc., vol. 141, No. 12, Dec. 1994.
High-Performance Self-Aligned P.sup.+ /N GaAs Epitaxial JFET's Incorporating AlGa As Etch-Stop Layer, authored by J.K. Abrokwah et al., p. 1529 in the IEEE Transactions on Electron Devices, vol. 37, No. 6, Jun. 1990.
Making a High--Yield, 0.33 Micron, MBE--Based G.alpha.As MMIC Production Process, authored by R.D. Remba et al., p. 90 in the proceedings of the 1994 U.S. Conference on GaAs Manufacturing Technology (MANTECH), May 1994.
Simplified Ohmic and Schottky Contact Formation for Field Effect Transistors Using the Single Layer Integrated Metal Field Effect Transistor (SLIMFET) Process, authored by G.C. DeSalvo et al., p. 314 in the IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 3, Aug., 1995.
All-Refractory GaAs FET Using Amorphous TiWSIx Source/Drain Metallization and Graded-InxGa 1-xAs Layers, authored by N.A. Papanicolaou et al., p. 7 in the IEEE Electron Device Letters, vol. 15, No. 1, Jan. 1994.
A New Fabrication Technology for AlGaAs/GaAs HEMT LSI's Using InGaAs Nonalloyed Ohmic Contacts, authored by S. Kuroda et al., p. 2196 in the IEEE Transactions on Electron Devices, vol. 36, No. 10, Oct. 1989.
A Highly Manufacturable 0.2 .mu.m AlGaAs/InGaAs PHEMT Fabricated Using the Single-Layer Integrated-Metal FET (SLIMFET) Process, authored by Charles K. Havasy et al., appearing in the IEEE Gallium Arsenide Integrated Circuit Symposium, Conference Proceedings, San Diego CA, Oct. 1995.
Ohmic Contacts to n -GaAs Using Graded Band Gap Layers of Ga1-xInx As Grown by Molecular Beam Epitaxy, authored by J.M. Woodall et al., p. 626 in the J. Vac. Sci. Technol. vol 19, No. 3, Sep./Oct 1981.
HEMT with Nonalloyed Ohmic Contact Using n.sup.+ -InGaAs Cap Layer, authored by S. Kuroda et al., p. 389 in the IEEE Electron Device Letters, vol EDL-8, No. 9, Sep. 1987.
Extremely Low Nonalloyed and Alloyed Contact Resistance Using an InAs Cap Layer on InGaAs by Molecular-Beam Epitaxy, authored by C.K. Peng et al., p. 429 in the J. Appl. Phys. vol. 64, No. 1, Jul. 1, 1988.
Non-Alloyed Ohmic Contacts to n-GaAs Using Compositionally Graded InxGa1-xAs Layers, authored by T. Nittono et al., pp. 1718-1722 in the Japanese Journal of Applied Physics, vol. 27, No. 9, Sep. 1988.
Extremely Low Contact Resistances for AlGaAs/GaAs Modulation-Doped Field-Effect Transistor Structures, authored by A. Ketterson et al., p. 2305 in the J. Appl. Phys. vol 57, No. 6, Mar. 1985.
Single-Cycle Lithography Process for Both Large and Sub-Half Micron Features, authored by J.S. Sewell et al., p. 177 in the SPIE, vol. 1671, 1992.
A Combined Electron Beam/Optical Lithography Process Step for the Fabrication of Sub-Half-Micron-Gate-Length MMIC Chips, authored by J.S. Sewell et al., and appearing in the Conference Proceedings of the Fourth National Technology Transfer Conference and Exposition, Dec. 7-9, 1993, Anaheim, California, NASA Conference Publication 3249, vol. 1, p. 54.

Affiliated with

Also associated with

Rating

Field effect transistor process with semiconductor mask, single does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Field effect transistor process with semiconductor mask, single , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field effect transistor process with semiconductor mask, single will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-324988