Field effect transistor having impurity regions of different dep

Details Field effect transistor having impurity regions of different dep Field effect transistor having impurity regions of different dep

1993-02-02

1994-01-04

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257306, 257327, 257344, 257346, H01L 2968, H01L 2978, H01L 2992

Patent

active

052763447

ABSTRACT:
Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

REFERENCES:
patent: 4702797 (1987-10-01), Shimano et al.
patent: 4978628 (1990-12-01), Rosenthal
patent: 5005072 (1991-04-01), Gonzalez
patent: 5108940 (1992-04-01), Williams
Wakamiya et al, "Novel Stacked Capacitor Cell for 64Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70.
Kaga et al, "Crown-Type Stacked Capacitor Cell for 64 MDRAM Operative at 1.5V", The Second Proceeding of the 37th Joint Lecture Meeting on Applied Physics, 1990, p. 582.
Koyanagi et al, "Novel High Density, Stacked Capacitor MOS RAM", 1978 International Electron Devices Meeting Technical Digest, pp. 348-351.

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