Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-21
2001-09-11
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000
Reexamination Certificate
active
06288433
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming transistor gates and to transistor constructions.
BACKGROUND OF THE INVENTION
As transistor gate dimensions are reduced and the supply voltage remains constant, the lateral field generated in MOS devices increases. As the electric field becomes strong enough, it gives rise to so-called “hot-carrier” effects in MOS devices. This has become a significant problem in NMOS devices with channel lengths smaller than 1.5 micron, and in PMOS devices with sub-micron channel lengths.
High electric fields cause the electrons in the channel to gain kinetic energy, with their energy distribution being shifted to a much higher value than that of electrons which are in thermal equilibrium within the lattice. The maximum electric field in a MOSFET device occurs near the drain during saturated operation, with the hot electrons thereby becoming hot near the drain edge of the channel. Such hot electrons can cause adverse effects in the device.
First, those electrons that acquire greater than or equal to 1.5 eV of energy can lose it via impact ionization, which generates electron-hole pairs. The total number of electron-hole pairs generated by impact ionization is exponentially dependent on the reciprocal of the electric field. In the extreme, this electron-hole pair generation can lead to a form of avalanche breakdown. Second, the hot holes and electrons can overcome the potential energy barrier between the silicon and the silicon dioxide, thereby causing hot carriers to become injected into the gate oxide. Each of these events brings about its own set of repercussions.
Device performance degradation from hot electron effects have been in the past reduced by a number of techniques. One technique is to reduce the voltage applied to the device, and thus decrease in the electric field. Further, the time the device is under the voltage stress can be shortened, for example, by using a lower duty cycle and clocked logic. Further, the density of trapping sites in the gate oxide can be reduced through the use of special processing techniques. Also, the use of lightly doped drains and other drain engineering design techniques can be utilized.
Further, it has been recognized that fluorine-based oxides can improve hot-carrier immunity by lifetime orders of magnitude. This improvement is understood to mainly be due to the presence of fluorine at the Si/SiO
2
interface reducing the number of strained Si/O bonds, as fewer sites are available for defect formation. Improvements at the Si/SiO
2
interface reduces junction leakage, charge trapping and interface trap generation. However, optimizing the process can be complicated. In addition, electron-trapping and poor leakage characteristics can make such fluorine-doped oxides undesirable and provide a degree of unpredictability in device operation. Use of fluorine across the entire channel length has been reported in, a) K. Ohyu et al., “Improvement of SiO
2
/Si Interface Properties by Fluorine Implantation”; and b) P. J. Wright, et al., “The Effect of Fluorine On Gate Dielectric Properties”.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a transistor includes semiconductive material and a transistor gate having gate oxide positioned therebetween. The gate has opposing gate edges and a central region therebetween. A source is formed laterally proximate one of the sate edges and a drain is formed laterally proximate the other of the gate edges. Chlorine is provided within the gate oxide layer between the semiconductive material and the transistor gate.
Another aspect of the invention provides a transistor comprising semiconductive material and a transistor gate having gate oxide positioned therebetween. The gate has opposing gate edges and a central region therebetween, and the gate oxide has opposing edges substantially laterally aligned with the opposing gate edges. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. At least one of fluorine or chlorine is concentrated in the gate oxide layer between the semiconductive material and the transistor gate more proximate at least one of the gate edges than the central region.
According to another aspect, a transistor includes semiconductive material and a transistor gate having sate oxide positioned therebetween, and the gate has opposing gate edges. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. First insulative spacers are formed proximate the gate edges and elevationally below the top of the transistor gate, and the first insulative spacers are doped with at least one of chlorine or fluorine. Second insulative spacers are formed over the first insulative spacers.
Yet another aspect provides a transistor comprising semiconductive material and a transistor gate having gate oxide positioned therebetween, and the gate has opposing gate edges. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. First insulative spacers are formed proximate the gate edges, and the first insulative spacers are doped with at least one of chlorine or fluorine. Second insulative spacers are formed over substantially all of respective outwardly exposed surfaces of the first insulative spacers.
REFERENCES:
patent: 3933530 (1976-01-01), Mueller et al.
patent: 4949136 (1990-08-01), Jain
patent: 5225355 (1993-07-01), Sugino
patent: 5243212 (1993-09-01), Williams
patent: 5369297 (1994-11-01), Kusunoki
patent: 5382533 (1995-01-01), Ahmad et al.
patent: 5506278 (1996-04-01), Suzuki et al.
patent: 5516707 (1996-05-01), Loh et al.
patent: 5571734 (1996-11-01), Tseng et al.
patent: 5599726 (1997-02-01), Pan
patent: 5672525 (1997-09-01), Pan
patent: 5672544 (1997-09-01), Pan
patent: 5705409 (1998-01-01), Witek
patent: 5710450 (1998-01-01), Chau et al.
patent: 5714788 (1998-02-01), Ngaoram
patent: 5716875 (1998-02-01), Jones, Jr. et al.
patent: 5721170 (1998-02-01), Bergemont
patent: 5750435 (1998-05-01), Pan
patent: 5763312 (1998-06-01), Jeng et al.
patent: 5807771 (1998-09-01), Vu et al.
patent: 5814863 (1998-09-01), Pan
patent: 5831319 (1998-11-01), Pan
patent: 5851890 (1998-12-01), Tsai et al.
patent: 5923949 (1999-07-01), Gardner et al.
patent: 6004852 (1999-12-01), Yeh et al.
patent: 6087239 (2000-07-01), Juengling
patent: 42 29 574 A1 (1992-09-01), None
patent: 42 29 574 A1 (1993-03-01), None
patent: 01272161 (1989-10-01), None
patent: 02173611 (1990-06-01), None
patent: 04062974 (1992-02-01), None
Ohyu, K., et al., “Improvement Of SiO2/Si Interface Propertiesby Fluorine Implantation”,Extended Abstracts of the 20th Conference on Solid State Devices and Materials, Tokyo, JP, pp. 607-608 (1988).
Wright, PJ., et al., “The Effect Of Fluorine On Gate Dielectric Properties”,I.E.E.E., pp. 87-574—87-576 (1987).
Akram Salman
Ditali Akram
Micro)n Technology, Inc.
Nadav Ori
Thomas Tom
Wells, St. John, Roberts Gregory & Matkin P.S.
LandOfFree
Field effect transistor having improved hot carrier immunity does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Field effect transistor having improved hot carrier immunity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field effect transistor having improved hot carrier immunity will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2528683