Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-20
2002-04-09
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S342000, C257S408000, C257S409000, C257S490000, C257S491000, C257S494000, C257S495000, C438S282000, C438S284000, C438S286000, C370S445000, C370S901000, C709S241000
Reexamination Certificate
active
06369424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to field effect transistors and, more particularly, to a technique for improving the breakdown withstand capacity of a field effect transistor.
1. Prior Art
Reference number
101
in
FIG. 10
represents a MOSFET according to the related art. In the MOSFET
101
, an n
−
-type silicon single crystal is grown on an epitaxial basis on a surface of an n
+
-type silicon single crystal substrate
105
to form a drain layer
111
. A p-type base diffusion layer
112
is formed in the drain layer
111
through a photolithographic step and a diffusion step.
An n
+
-type source region
114
is formed in the base diffusion layer
112
, and a channel region
115
is formed between a peripheral portion of the base diffusion layer
112
and a peripheral portion of the source region
114
on the top surface of the drain region
111
.
The base diffusion layer
112
has a square configuration, and a plurality of base diffusion layers
112
are provided on the top surface of the drain layer
111
such that the sides thereof face each other.
A gate oxide film
121
is formed on a surface of the channel region
115
, and a gate electrode film
131
is formed on a surface of the gate oxide film
121
.
A source electrode film
132
is formed on the base diffusion layer
112
and source region
114
. The source electrode film
132
and gate electrode film
131
are insulated from each other by a layer insulation film
122
.
When the source electrode film
132
is formed, a gate pad
135
is formed simultaneously. The gate pad
135
is isolated from the source electrode film
132
and is connected to the gate electrode film
131
. The MOSFET
101
is encapsulated in a resin package. One end of a bonding wire is connected to the gate pad
135
which is thereby extended to the outside of the package as a gate terminal.
A drain electrode film
133
is formed on the back surface of the drain layer
111
. The source electrode film
132
and drain electrode film
133
are also extended to the outside as a source terminal and a drain terminal, respectively.
In the MOSFET
101
having the above-described structure, when a positive voltage is applied to the gate electrode film
131
with the source electrode film
132
grounded and a positive voltage applied to the drain electrode film
133
, an n-type inversion layer is formed on a surface of the channel region
115
; the source region
114
and drain layer
111
are connected by the inversion layer; and a current flows from the drain electrode film
133
to the source electrode film
132
.
Then, the inversion layer vanishes when the voltage at the gate electrode film
132
approaches the ground potential, and this cuts off the current.
In general, a parasitic diode is formed by a p-n junction between the drain layer
111
and base diffusion layer
112
. When the potential of the source electrode film
132
is higher than that of the drain electrode film
133
, the parasitic diode is forward-biased to cause a current to flow from the source electrode film
132
to the drain electrode film
133
.
When a current flows through a parasitic diode as described above, minority carriers are injected into the drain layer
111
. When the parasitic diode is reverse-biased from the forward-biased state, the minority carriers that have been injected into the drain layer
111
flow into the base diffusion layer
112
, which may cause breakdown of a region outside the periphery of an active region
141
because no base diffusion layer exists in that region.
SUMMARY OF THE INVENTION
The present invention was conceived to solve the above described problem with the related art, and it is an object of the invention to provide a field effect transistor having a high breakdown withstand capacity.
In order to solve the above-described problem, according to the present invention, there is provided a field effect transistor having: a substrate of one conductivity type; a drain region of the same conductivity type as that of the substrate, provided on the substrate; a fixed potential diffusion layer of a conductivity type different from that of the drain layer, in the form of a ring provided inside the drain layer and on the side of a top surface thereof; an active region which is a part of the drain layer and which is a region located inside the fixed potential diffusion layer in the drain layer; a base diffusion layer of a conductivity type different from that of the drain layer, provided on the side of the top surface in the active region;
a channel diffusion layer of the game conductivity type as that of the base diffusion layer, provided on the side of the top surface in the active region, connected to the base diffusion layer; a source diffusion layer of conductivity type different from that of the base diffusion layer, provided on the side of the top surface in the base diffusion layer and on the side of the top surface in the channel diffusion layer; a gate insulation film provided on the surface of at least a part of the channel diffusion layer between the periphery of the source diffusion layer and the periphery of the channel diffusion layer; a gate electrode film provided on the gate insulation film; a drain electrode film electrically connected to the drain layer; and a source electrode film electrically connected to the source diffusion layer, the base diffusion layer and the fixed potential diffusion layer.
In a field effect transistor according to the current invention, a guard ring diffusion layer of a conductivity type different from that of the drain layer may be provided in the drain layer outside the fixed potential diffusion layer in non-contact with the fixed potential diffusion layer such that it surrounds the fixed potential diffusion layer, and the guard ring diffusion layer may be at a floating potential.
The guard ring diffusion layer may be put at a floating potential by not connecting a guard ring electrode to the source electrode, the drain electrode and gate electrode to which a voltage is applied. Alternatively, a metal film in electrical connection to the guard ring diffusion layer may be provided on the guard ring diffusion layer.
Further, a field effect transistor according to the current invention may have a plurality of guard ring diffusion layers in non-contact with each other and may have a configuration in which a guard ring diffusion layer is surrounded by a guard ring diffusion layer located outside thereof.
Furthermore, a field effect transistor according to the invention may have an insulation film provided on the drain layer outside the active region, a gate pad electrically connected to the gate electrode film and an external terminal will be fixed to, provided on the insulation film and a pad diffusion film of a conductivity type different from that of the drain layer, provided in the drain layer directly under the gate pad, and the pad diffusion layer may be connected to the guard ring diffusion layer adjacent to the fixed potential diffusion layer.
The present invention has a configuration as described above in which an active region is surrounded by a fixed potential diffusion layer. The fixed potential diffusion layer is connected to a source electrode, and a part of minority carriers injected in the active region which are present at the periphery of the active region can be efficiently collected. This prevents the minority carriers from concentrating at the periphery of the active region and makes it possible to provide a MOSFET having a high breakdown withstand capacity.
A gate pad is provided outside the fixed potential diffusion layer, and a pad diffusion layer of a conductivity type different from that of a drain layer is formed in the drain layer located under the gate pad. The pad diffusion layer is connected to an innermost guard ring diffusion layer to be put at a floating potential. As a result, the pad diffusion layer serves as a part of the guard ring diffusion layer to provide an increased breakdown voltage.
Since no co
Miyakoshi Nobuki
Nakamura Hideyuki
Armstrong Westerman & Hattori, LLP.
Kang Donghee
Shindengen Electric Manufacturing Co. Ltd.
Thomas Tom
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