Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-04-26
2011-04-26
Smith, Matthew S (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S240000, C438S289000, C438S303000, C438S525000, C257SE21252, C257SE21577
Reexamination Certificate
active
07932166
ABSTRACT:
By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be significantly increased. For instance, non-conformal PECVD techniques may be used for forming highly stressed silicon nitride in a non-conformal manner, thereby achieving higher transistor performance for otherwise identical stress conditions.
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patent: 7052946 (2006-05-01), Chen et al.
patent: 2005/0158955 (2005-07-01), Yang et al.
patent: 2007/0096220 (2007-05-01), Kim et al.
patent: 2008/0122003 (2008-05-01), Fang et al.
patent: 1 717 864 (2006-11-01), None
Widmann et al., “Technologie hochintegrierter Schaltungen,” p. 315.
Feustel Frank
Frohberg Kai
Werner Thomas
Advanced Micro Devices , Inc.
Parker John M
Smith Matthew S
Williams Morgan & Amerson P.C.
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