Field effect transistor formed on SOI substrate

Details Field effect transistor formed on SOI substrate Field effect transistor formed on SOI substrate

2002-10-31

2004-11-30

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S382000, C257S388000

Reexamination Certificate

active

06825535

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a MOS field effect transistor (hereinafter abbreviated as “MOSFET”) fabricated on a substrate such as an SOI substrate wherein a silicon thin film is formed on an insulator.
A MOSFET formed on a conventional SOI substrate is formed using a process similar to a process for forming a MOSFET on a normal silicon substrate according to such a process as disclosed in Table 3 of Lisa et al., IEDM Technical Digest, p723-p726, 1993.
In the MOSFET fabricated according to such a manufacturing process, the thickness of an SOI layer is thinned to cope with a so-called short channel effect (SCE) wherein a threshold voltage (Vth) is reduced as a gate length becomes short with micro-fabrication or scale-down of the MOSFET, thereby improving an SCE problem.
A result of an experiment for suppressing the short channel effect by thinning the thickness of the SOI layer of the MOSFET has been shown in FIG. 9 in N. Kistler et al., Solid State Electronics, Vol. 30, No. 4, p445-454 (1996).
Further, a contact resistance is involved in a problem caused by the micro-fabrication of the MOSFET as a point related to a current driving capacity (hereinafter abbreviates as “driving capacity”) of the MOSFET. A surface (contact) in which a diffused layer and a contact conductive layer contact with each other, is a window for transferring a signal from the diffused layer to a source or gate electrode via the contact conductive layer. A contact resistance and a diffused layer resistance serve as series parasitic resistances for a channel. Since the components of the contact resistance and diffused layer resistance relatively increase with the scale-down of the MOSFET, a voltage effectively applied across the channel is lowered and hence the driving capacity is reduced.
It is understood that a reduction in contact resistance and the thinning of an SOI layer are needed to prevent the reduction in driving capacity with the scale-down of the MOSFET formed on the substrate having the silicon layer formed on the insulator, like the SOI substrate or the like as described above.
However, when, even if the thinning of the SOI layer and the reduction in the contact resistance are simply made, other factors related to these factors vary and influences the driving capacity, it is very difficult to most effectively prevent the reduction in driving capacity. This is just conceivable where a partial structure related to the driving capacity of the MOSFET is taken into consideration.
The partial structure of the MOSFET is one related to the driving capacity. However, the partial structure is complex in configuration and a plurality of factors are considered to relate to one another as to the determination of the driving capacity. It is therefore conceivable that the simple control of one factor alone could make it difficult to most effectively suppress the reduction in driving capacity.
SUMMARY OF THE INVENTION
The present invention provides a MOSFET capable of thinning an SOI layer and effectively suppressing a reduction in driving capacity thereof due to a contact resistance.
A field effect transistor of the present invention comprises a silicon layer formed on an insulator, a diffused layer formed by diffusing dopant from a part of a surface of the silicon layer up to the insulator, a silicide layer formed toward the insulator side from a surface of the diffused layer so as to have a thickness less than or equal to that of the diffused layer, a contact conductive layer formed on the surface of the silicide layer, a gate insulating layer formed on the silicon layer, a gate electrode formed on the gate insulating layer and a sidewall formed on a side surface of the gate electrode. The shortest distance X between surfaces opposed to each other, of the contact conductive layer and the sidewall satisfies a relation represented by the following expression (1):
R
(
slc
)×10
6
×(1
+Tslc/Tsoi
)≦
X
≦200
/rs.
  Expression (1)
In the expression (1), X indicates the shortest distance (&mgr;m) between the mutually-opposed surfaces of the contact conductive layer and the sidewall. R(slc) indicates a contact resistance (&OHgr;·cm
2
) of a boundary surface between the silicide layer and the diffused layer. Tslc indicates the thickness (&mgr;m) of the silicide layer. Tsoi indicates the thickness (&mgr;m) of the silicon layer and rs indicates a series resistance (&OHgr;/) of the silicide layer.


REFERENCES:
patent: 4477963 (1984-10-01), Cogan
patent: 5192714 (1993-03-01), Suguro et al.
patent: 2002/0056887 (2002-05-01), Horstmann et al.
Ben G. Streetman, Solid state Electronic Devices, 4th ed. (1995), p. 354, Prentice-Hall, Inc., Upper Saddle River, New Jersey 07458.*
Lisa T. Su et al., “Optimization of Series Resistance in Sub-0.2 um SOI Mosfets,” IEDM Technical Digest, p. 723-726, 1993.
Neal Kistler et al., “Scaling Behavior of Sub-Micron Mosfets on Fully Depleted SOI,” Solid-State Electronics vol. 39, No. 4, pp. 445-454, 1996.
Table 4 Applied Physics, vol. 70, No. 9, 2001.

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