Field effect transistor core memory switching system and method

Details Field effect transistor core memory switching system and method Field effect transistor core memory switching system and method

1981-07-20

1984-07-31

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Signals

365209, 365230, G11C 702

Patent

active

044634498

ABSTRACT:
A core memory system includes a plurality of word lines strung through a core memory array and a plurality of field effect transistors coupling respective ones of the word select lines to an address decoding circuit. In one embodiment of the invention, the field effect transistors are utilized in conjunction with a transformer selection system. In the transformer selection system, the drain electrodes of each field effect transistor are connected in series with respective ones of a plurality of secondary windings of a transformer. The system includes a plurality of such transformers, the primary windings of the various transformers being selected in response to a first decoder. The gates of the respective field effect transistors are selected in response to a second decoder. A plurality of balanced sense/inhibit line pairs strung through the core array are selectively multiplexed by means of field effect coupling transistors to the inputs of a single sense amplifier, wherein all sense/inhibit lines are initially coupled by means of field effect transistors to the inputs of the sense amplifier. Prior to applying select line currents, all of the balanced sense/inhibit lines except the selected one are turned off in order to minimize coupling of parasitic signals onto the selected sense/inhibit line pair.

REFERENCES:
patent: 4358832 (1982-11-01), Warner

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