Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-03-28
2001-11-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S157000, C438S158000
Reexamination Certificate
active
06316296
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fine, high-performance dual gate field-effect transistor, and to a method of manufacturing the transistor.
2. Description of the Prior Art
As transistors become increasingly fine, it has given rise to a pronounced short channel effect in which fluctuations in gate length produce variations in threshold values. The use of a dual gate structure is known to be an optimum way of preventing the short channel effect (see Japanese Patent Publication Gazette No. 62-1270). However, as far as the present inventors know, no industrial method of fabricating a field-effect transistor with a dual gate structure has actually been proposed. In particular, no transistor has been proposed in which a group of an upper gate and a lower gate and another group of a source and a drain are self-aligning and the parasitic capacitance that hinders high-speed operation in a field-effect transistor is minimized, nor has a method of commercially producing such a transistor been proposed.
The reason for this is that in the prior art procedure used to fabricate a MOS transistor, a gate is fabricated in a first photolithography step and a source and a drain are formed using the gate as a mask so that the source and drain self-aligns with the gate. That is, the fact that there is no planar overlay between the gate and the source and between the gate and the drain is utilized.
However, when the gate comprises an upper and a lower gate, it is difficult to form the two gates so that they self-align. If, for example, the upper gate is formed first by the photolithography step, it is difficult to then form the lower gate, a source and a drain so that they align with the upper gate. This is because while one group of the upper and lower gates has to be formed as a planar overlay, another group of the source and drain has to be formed so that the another group does not overlay the one group, hence there is the difficulty in trying to use a single process to form both groups. Because of this difficulty, dual gate field-effect transistors are usually formed using two or more photolithography steps. However, the drawback with using two or more process steps is that the devices are more likely to be defective owing to errors in mask alignment.
This invention was accomplished to overcome the foregoing problems and has as an object to provide a fine, high-performance, self-aligning, dual gate field-effect transistor, and a method of commercially manufacturing the transistor.
SUMMARY OF THE INVENTION
For achieving this object, the invention provides a dual gate structure field-effect transistor comprising:
an SOI substrate comprised of a semiconductor support substrate, a buried insulation layer formed on the support substrate and an SOI semiconductor layer formed on the insulation layer,
a trench formed in the SOI substrate so as to extend from an upper surface of the SOI substrate through the SOI semiconductor layer and the buried insulation layer to the semiconductor support substrate, thereby dividing the SOI semiconductor layer into two SOI semiconductor layer regions that form a source electrode and a drain electrode,
a gate electrode formed in the trench in contact with the buried insulation layer and the semiconductor support substrate, thereby self-aligning with the source electrode and drain electrode,
a gate insulation layer formed on the gate electrode in contact with the buried insulation layer around the trench,
a semiconductor conduction channel layer formed on the gate insulation layer in contact with the two SOI semiconductor layer regions around the trench,
an upper gate insulation layer formed on an upper surface of the semiconductor conduction channel layer and a SOI semiconductor layer inside surface defining the trench, and
an upper gate electrode formed in the trench so as to have a bottom surface and side surface covered by the upper gate insulation layer, thereby self-aligning with the gate electrode, source electrode and drain electrode.
The above object is also achieved by a method of manufacturing a dual gate structure field-effect transistor, comprising the steps of;
forming a trench in an SOI substrate comprised of a semiconductor support substrate, a buried insulation layer formed on the support substrate and an SOI semiconductor layer formed on the insulation layer, so as to extend from an upper surface of the SOI substrate through the SOI semiconductor layer and the buried insulation layer to the semiconductor support substrate, thereby dividing the SOI semiconductor layer into two SOI semiconductor layer regions that form a source electrode and a drain electrode,
forming a gate electrode constituted of low resistance material in a portion of the trench in contact with the buried insulation layer, thereby self-aligning with the source electrode and drain electrode,
forming a gate insulation layer on the gate electrode in contact with the buried insulation layer around the trench,
forming a semiconductor conduction channel layer on the gate insulation layer in contact with the two SOI semiconductor layer regions around the trench,
forming an upper gate insulation layer on an upper surface of the semiconductor conduction channel layer and a SOI semiconductor layer inside surface defining the trench, and
forming an upper gate electrode in the trench so as to have a bottom surface and side surface covered by the upper gate insulation layer, thereby self-aligning with the gate electrode, source electrode and drain electrode.
The method of manufacturing the field-effect transistor also includes, prior to forming the upper gate electrode, forming a gate extraction region on the SOI substrate that is connected with the trench and has an opening that extends to the gate electrode, and filling the gate extraction region with electrode material to form the upper gate electrode that electrically connects the gate electrode.
The method of manufacturing the field-effect transistor also includes, preceding the formation of the upper gate insulation layer, forming the gate extraction region by entrenching at a position where the gate extraction region abuts or overlays the gate electrode, so that the upper gate extraction region self-aligns.
The method of manufacturing the field-effect transistor also includes removing down to the buried insulation layer portions other than the source electrode, drain electrode, upper gate electrode and gate extraction region to expose the gate electrode.
Since the formation of the gate electrode and upper gate electrode is self-aligning, only one photolithography step is required, simplifying the fabrication process, thereby facilitating commercial fabrication while at the same time reducing costs. Also, since the formation of the two gate electrodes self-align, errors arising from mask misalignment are eliminated, so the product yield is improved. In addition, the self-alignment makes it possible to achieve a shorter gate length using the same lithographic feature dimension, improving transistor performance.
Further features of the invention, its nature and various advantages will become more apparent from the accompanying drawings and following detailed description of the invention.
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Denton, J.P., et al., “Fully depleted dual-gated thin
Agency of Industrial Science & Technology, Ministry of Internati
Niebling John F.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Whitmore Stacy A
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