Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-19
2004-02-10
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S345000
Reexamination Certificate
active
06690060
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and particularly to realization of a super miniaturized insulated gate field effect transistor with a larger current and a superhigh operation speed.
2. Description of the Related Art
Enhancement of performance of insulated gate field effect transistors constituting an ultrahigh-density integrated circuit device (hereinafter referred to simply as “MOS”) has been achieved by reducing transistor area and gate size so as to attain the merits of reduction in power supply voltage used and reduction in parasitic capacitance according to the scaling rule. At present, super miniaturized MOSs with a gate length of not more than 160 nm have also been put to practical use. In these super miniaturized MOSs, reduction of the source and drain junction depth has also been tried attending on the reduction in the gate length, and a shallow junction depth of not more than 30 nm has been attained at present. In reducing the source and drain junction depth, reduction of the resistance of a source diffusion layer is essential to realization of a large current while restraining the so-called short channel effect, namely, an abrupt lowering of threshold voltage attendant on the reduction of the gate length.
FIG. 2
is a sectional view schematically showing a conventional super miniaturized MOS, and
FIG. 3
shows an impurity distribution in the depth direction in high concentration source and drain shallow junctions
4
,
5
(called “extension”) in FIG.
2
. In
FIG. 2
, in the case of an N conductive type MOS, a gate insulation film
2
is provided on the surface of a P conductive type Si substrate
1
, and a gate electrode
3
is provided thereon. N conductive type source and drain shallow junction diffusion layers
4
,
5
and so-called pocket diffusion layer regions
7
which are high concentration P conductive type impurity diffusion layers for preventing the so-called short channel effect are introduced by using the gate electrode
3
as an implantation mask. Further, source and drain diffusion layers
9
,
10
of N conductive type and deep junction are introduced by using a gate side wall insulation film
8
as an implantation mask. In the figure, numeral
11
denotes a silicide film,
12
a surface protective insulation film,
13
a source electrode, and
14
denotes a drain electrode.
The source and drain shallow junction diffusion layers are fabricated conventionally by the following steps. (1) A high concentration impurity is introduced by low acceleration energy ion implantation using the gate electrode as an implantation(screen) mask; (2) then, the pocket regions are provided by ion implantation; (3) further, the source and drain diffusion layers of deep junction are provided by ion implantation using the gate electrode side wall insulation film as a mask; and (4) thereafter, activation of the implanted ions is carried out by a high-temperature short-period annealing method. The short-period anneal is adopted in order to achieve the activation while retaining the steep impurity distribution obtained upon ion implantation, through minimizing the spreading of junction depth due to thermal diffusion of implanted impurities.
However, further reductions in the junction depth and the resistance of the diffusion layers cannot be achieved by only the short period annealing at high temperature. A principal reason is based on the so-called transient enhanced diffusion phenomenon, namely, enhanced diffusion under a relatively low temperature condition of not more than 900° C. due to the presence of interstitial Si and vacancies generated upon ion implantation. The generation of the interstitial Si and vacancies is inevitable also in the subsequent ion implantation for forming the deep source and drain regions, and enhanced diffusion in the shallow junction regions is further augmented. The generation of interstitial Si is seen also in a thermal oxidation step, and is called oxidation enhanced diffusion phenomenon, so that it is very difficult to restrain the enhanced diffusion phenomenon in the subsequent steps.
FIG. 3
shows the results of measurement by secondary ion mass spectrometry of impurity distribution in the range from the surface to the inside of a substrate upon ion implantation of boron (B) into an Si single crystal substrate at an acceleration energy of 3 keV and a dose of 1×10
15
/cm
2
and after a short anneal at 1000° C. for 10 sec. As is clear from the figure, a tailing phenomenon of the impurity distribution is observed in spite of the low acceleration energy implantation, and it is very difficult to form a shallow junction even with the short period anneal. It is also apparent that impurity concentration gradually and monotonously decreases from the surface toward the depth direction, in other regions than the vicinity of the surface. Namely, the impurity distribution shape obtained at present is far from the rectangular distribution shape with a high concentration of 10
20
/cm
3
, which is considered to be an ideal impurity distribution for realizing a low diffusion layer resistance while maintaining a shallow junction.
Therefore, in order to achieve a small size and a larger current with a miniaturized MOS, realization of an optimum impurity distribution offering both shallower junction and lower resistance to the present source and drain junctions is indispensable.
As another phenomenon hampering the provision of source and drain extension junctions with shallow junction and high concentration rectangular distribution, there is known the so-called channeling phenomenon in which implanted ions pass through more than the penetration distance determined by the acceleration energy, because the Si crystal lattice spacing depends on the crystal orientation. In order to prevent the spreading of the impurity concentration distribution due to the channeling phenomenon, there have been known slant angled ion implantation and implantation of a large amount of an ion neutral to Si such as Ge to preliminarily amorphousize the surface region, thereby preventing the channeling phenomenon at the time of ion implantation for forming extension junctions. However, the ion implantation for amorphousizing is also attended by the generation of interstitial Si and vacancies, and it is difficult to realize the formation of an ideal shallow junction. Further, in recrystallization of an amorphousized region by heat treatment, recovery to a perfect crystal is difficult, and a junction formed in the region is affected by crystalline defects nonnegligibly and is attended by generation of junction leakage current.
A technique of using In as a means for preventing the channeling phenomenon is seen in Japanese Patent Laid-Open No. Hei 11-87706. In the publication, the following procedure is adopted: (1) In is implanted though the entire surface of an active region of an N channel MOS transistor (referred to as NMOS) or by using a gate electrode as a mask to achieve amorphousizing; (2) As ion is implanted to form extension junctions; (3) P ion is implanted to form deep source and drain diffusion layers; and (4) heat treatment is carried out for activation of introduced impurities. The purpose of the above technique is to form the deep source and drain diffusion layers to be shallower layers by utilizing the phenomenon of attraction of P by In through setting the implantation penetrate distance of In at a depth between the extension junction and the deep source and drain diffusion layers. Namely, in the above technique, amorphousizing and the phenomenon of attraction of P by In are used for obtaining shallower junctions. Incidentally, according to the description of the above technique, activation coefficient is higher with P than with As, and As is smaller than P in mass; however, this is contrary to the fact, and As ion implantation is ordinarily used also for formation of deep source and drain diffusion layers.
Another technique of applying the phenomenon of mutual
Horiuchi Masatada
Takahama Takashi
Flynn Nathan J.
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Quinto Kevin
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