Field effect transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S361000, C257S355000, C257S335000

Reexamination Certificate

active

07067878

ABSTRACT:
A MOS field effect transistor. A field relaxation layer of a gate overlap structure is disposed in contact with a drain region for the purpose of relaxation of the electric field by increasing a distance between the field relaxation layer and a high-density layer. The electric field relaxation can further be promoted because the equipotential lines are bent by a gate insulation film. A punch-through stopper layer of a gate overlap structure is disposed in contact with a source region for suppressing spreading of a depletion layer toward the source region. The length of a gate electrode can be realized in a miniaturized size.

REFERENCES:
patent: 5438215 (1995-08-01), Tihanyi
patent: 5578509 (1996-11-01), Fujita
patent: 5594264 (1997-01-01), Shirahata et al.
patent: 04-241463 (1992-08-01), None
patent: A-05-110080 (1993-04-01), None
patent: 05-129602 (1993-05-01), None
patent: A-05-129602 (1993-05-01), None
patent: 06-021441 (1994-01-01), None
patent: 6-310717 (1994-11-01), None
patent: 7-007154 (1995-01-01), None
patent: A-07-086580 (1995-03-01), None
patent: A-11-121742 (1999-04-01), None
IEDM 89, “Asymmetrical Halo Source GOLD drain (HS-GOLD) Deep Sub-half Micron n-MOSFET Design for Reliability and Performance” pp. 617-620.

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