Field-effect transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C438S261000

Reexamination Certificate

active

06642591

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field-effect transistor formed on a silicon substrate.
2. Description of the Prior Art
The foundation of today's information society is formed by large-scale, integrated high-speed computers and storage devices, most of which are ultralarge-scale integrated circuits (ULSIs) fabricated on a silicon substrate. More specifically, these are integrations of the type of transistor called a MOSFET, which stands for Metal-Oxide-Semiconductor Field-Effect Transistor. These are fabricated on a silicon substrate by using doping to form source and drain regions separated by the channel region. A gate insulation layer of silicon oxide (SiO
2
) is formed on the surface of the channel region, on top of which a gate electrode (of polysilicon doped to decrease the sheet resistance, or of a metal such as molybdenum) is formed to apply the electric field. Degradation of the gate insulation layer results in breakdown of the insulation and leakage current, making it impossible for the device to perform as a transistor.
Over the years, ULSIs based on the MOSFET have made great advances in integration, but in recent years the physical limit of device operation has become a problem. Particularly with respect to the MOSFET, a major problem is that the SiO
2
(relative dielectric constant of 3.9) currently used as the gate insulation layer material is not able to satisfy future needs of integration-based device scaling and lower power consumption. A thinner gate insulation layer is required in order to increase integration, improve performance and reduce power consumption. However, when the SiO
2
layer thickness is reduced to be in the order of 10
−9
m, it becomes readily susceptible to current tunnelling, and as such can no longer be regarded as a good insulator. Research is still underway to find a suitable material to use instead of SiO
2
, but the candidates are perovskite oxides that contain a transition metal, such as SrTiO
3
, for example.
Forming the gate insulation layer using an insulating material having a high relative dielectric constant, makes it possible to obtain a static capacitance on a par with that of a physically thicker SiO
2
layer. Moreover, it would also enable fabrication of devices that are less prone to problems such as insulation breakdown. However, depending on the material used for the channel region at the boundary with the gate insulation layer, and the electrode material, there can be movement of the oxygen in the insulation layer, causing problems such as that it becomes impossible to obtain a suitable interface, the static capacitance of the gate is reduced by the generation of other oxides, and so forth.
An object of the present invention is to provide a field-effect transistor with good performance having the oxide gate insulator and the oxide gate electrode. Emplying an oxide for the electrode makes the gate insulator have its intrinsic properties.
SUMMARY OF THE INVENTION
To attain the above object, the present invention provides a field-effect transistor comprising: a silicon substrate; a channel region with a source region at one end of the channel region and a drain region at another end of the channel region formed on the silicon substrate; and a gate electrode provided on a gate insulation layer of a transition metal oxide having a perovskite structure formed at least on an upper surface of the channel region.
The object is also attained by a field-effect transistor having a double-gate MOS type structure comprising: a channel region; a source region and a drain region provided at each end of the channel region; one gate insulation layer formed at least on an upper surface of the channel region and another gate insulation layer formed at least on a lower surface of the channel region, each gate insulation layer being formed of a transition metal oxide having a perovskite structure; and a gate electrode provided on each of the gate insulation layers.
The field-effect transistor also includes one in which the transition metal oxide used to constitute the gate insulation layer has a relative dielectric constant of 4 or more at room temperature. The field-effect transistor also includes one in which the gate insulation layer is comprised of a Ti-containing perovskite structure transition metal oxide, including SrTiO
3
.
The field-effect transistor also includes one in which the gate electrode is formed of a perovskite structure transition metal oxide that has an electrical resistivity at room temperature that is not more than 100 &mgr;&OHgr;-cm and includes Re, Mo, or Ru oxide.
As described in the foregoing, in accordance with the present invention, using a perovskite structure transition metal oxide having a high relative dielectric constant for the gate insulation layer increases the gate capacitance and provides excellent drivability without having to reduce the thickness of the gate insulation layer. This makes it easier to control the layer thickness, and leakage current is decreased even at higher integration levels.
Moreover, for the gate electrode material deposited directly on the gate insulation layer, by selecting a material that has good crystalline matching properties with respect to the gate insulation material and has very low electrical resistivity, a field-effect transistor can be realized having gate insulation material characteristics on a par with intrinsic characteristics.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and following detailed description of the invention.


REFERENCES:
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patent: 5352624 (1994-10-01), Miwa et al.
patent: 5995359 (1999-11-01), Klee et al.
patent: 6207995 (2001-03-01), Gardner et al.
patent: 6262461 (2001-07-01), Marshall et al.
patent: 6278164 (2001-08-01), Hieda et al.
patent: 2001/0025976 (2001-10-01), Lee
patent: 64-061952 (1989-03-01), None
patent: 08-204191 (1996-08-01), None
patent: 08-274087 (1996-10-01), None
patent: 10-341003 (1998-12-01), None
patent: 11-261028 (1999-09-01), None

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