Field effect transistor

Details Field effect transistor Field effect transistor

1999-08-26

2002-11-19

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S496000, C257S356000, C257S409000, C438S574000, C438S579000

Reexamination Certificate

active

06483135

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Schottky gate field effect transistor (FET) that operates in the microwave region used for mobile communication, satellite communication, satellite broadcasting and the like.
2. Description of the Prior Art
In comparison with Si, compound semiconductors are known to have high electron mobilities. For example, the electron velocity of GaAs is approximately 6 times in the low electric field and 2 to 3 times in the high electric field as fast as that of Si. Such characteristics of high-speed electrons have been put to a good use in developing applications thereof to high-speed digital circuit elements or high-frequency analog circuit elements.
In a FET using a compound semiconductor, however, a gate electrode makes a Schottky junction with a channel layer of a substrate so that the electric field centers on a lower end (a circled field-centered section in
FIG. 14
) of the gate electrode on the drain side, which may cause breakdown. This is the matter of great concern, especially for a high-output FET that necessitates large signal operations.
Accordingly, several attempts have been hitherto made to prevent this field centralization on the edge section of the gate electrode on the drain side and improve characteristics to withstand voltage.
Among them, there is one attempt in which an overhanging section (referred to as a ‘field plate section’, hereinafter) is set in a gate electrode, and, under this, a dielectric film made of SiO
2
is formed.
FIG. 12
shows schematically the structure of the FET disclosed in Japanese Patent Application Laid-open No. 87773/1988, wherein a dielectric film
34
is buried in a section below a gate electrode
33
on the drain side. Such a dielectric film, if set, is generally considered to be able to suppress the field centralization on the edge section of the gate electrode
33
on the drain side.
In the above-mentioned conventional techniques, however, the dielectric film must be made thin for the purpose of obtaining a sufficient effect on the field relaxation so that the value of electrostatic capacitance of a capacitor that consists of a field plate section and a channel layer separated by the dielectric film becomes large. On the other hand, the reduction in the thickness of the dielectric film tends to lead to a problem that the breakdown of the dielectric film or the leakage of the current may take place.
Further, because there is a certain limit in making the dielectric film thin, the maximum value for the electrostatic capacitance naturally exists. Therefore, to attain a sufficient effect on the field relaxation, the length of the field plate section should be more than a certain length, for example, a gate length, which may cause a problem of lowering the gain characteristics. Moreover, in this instance, high-frequency characteristics worsen significantly and this may become a crucial problem, depending on the purpose of use thereof.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to overcome the above-mentioned problems associated with the prior art and provide a FET having high withstand voltage characteristics and good gain characteristics, together with excellent high-frequency characteristics.
In light of the above problems, the present invention provides a FET, comprising:
a semiconductor substrate with a channel layer being formed on its surface;
a source electrode and a drain electrode being formed at a distance on said semiconductor substrate; and
a gate electrode being placed between said source electrode and said drain electrode and making a Schottky junction with said channel layer; wherein:
said gate electrode is provided with an overhanging field plate section; and
between said field plate section and said channel layer, there is laid a dielectric film made of a high dielectric material with a relative permittivity of 8 or more.
In the FET of the present invention, because a dielectric film is laid between the field plate section and the channel layer, the field centralization which develops on the edge section of the gate electrode on the drain side is made to relax and spread over, improving characteristics of withstand voltage. This results from a fact that a capacitor that consists of the field plate section and the- channel layer separated by the dielectric film has a function to end the electric flux line starting from ionized donors.
In the FET of the present invention, as a material for the dielectric film laid between the field plate section and the channel layer, a material with a relative permittivity of 8 or more is utilized. Therefore, even when the dielectric film is made thick, a high electrostatic capacitance can be obtained and, in consequence, a sufficient effect on the field relaxation can be attained. For example, compared with a SiO
2
film being used in the prior art, the film thickness can be made about twice as much as the conventional thickness to obtain the same given electrostatic capacitance.
As described above, since the film thickness of the dielectric film in the present invention can be made greater than the conventional one, the breakdown of the dielectric film and the generation of the leakage current can be prevented and characteristics of withstand voltage of element can be improved.
Further, because the dielectric film with a high permittivity is laid therein, as mentioned above, even if the length of the field plate section is not very long, a sufficient effect on the field relaxation can be attained. For instance, the length of the field plate section can be shorter than the gate length. Therefore, high withstand voltage characteristics can be obtained, while the reduction of the gain characteristics is kept down.
Further, the present invention provides a FET comprising:
a semiconductor substrate with a channel layer being formed on its surface;
a source electrode and a drain electrode being formed at a distance on said semiconductor substrate; and
a gate electrode being placed between said source electrode and said drain electrode and making a Schottky junction with said channel layer; wherein:
said gate electrode is provided with an overhanging field plate section; and
between said field plate section and said channel layer, there is laid a dielectric film; and
when the relative permittivity and the film thickness of the dielectric film are denoted by ∈ and t (nm), respectively, one of the following conditions (1) and (2) is satisfied.
1<∈<5, and 25
<t/∈<
70,  (1)
5=∈<8, and 100
<t
<350.  (2)
In the prior art, it was difficult to achieve a sufficient effect on the field relaxation, while preventing the breakdown of the dielectric film directly under the field plate section and the leakage of the current at the same time.
The present invention attempts to overcome this, by looking into the relative permittivity and the film thickness of the dielectric film and defining the relation between there two.
When 1<∈<5 is satisfied, if t/∈ is less than 25, the breakdown of the dielectric film or the leakage current takes place. On the other hand, if t/∈ exceeds 70, a sufficient effect on the field relaxation cannot be attained. The relative permittivity and the film thickness mean the average values of the relative permittivity and the film thickness of the dielectric film directly under the field plate section, respectively. In the case that a plurality of dielectric films made of different materials are laid directly under the field plate section, a reduced value (t/∈)
RED
given by the following equation is used as the value of t/∈ thereof,
(
t
/∈)
RED
=t
1
/∈
1
+t
2
/∈
2
+ . . . +t
n
/∈
n
(n is an integer that is equal to or more than 2). dielectric films made of different materials are laid directly under the field plate section, a reduced value (t/∈)
RED
given by the following equation is used as the value of t/∈ thereof,

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